{"title":"A 220 mW 1 Gb/s 1024-bit rate-1/2 low density parity check code decoder","authors":"A. Blanksby, C. Howland","doi":"10.1109/CICC.2001.929780","DOIUrl":null,"url":null,"abstract":"A 1024 bit rate-1/2 Low Density Parity Check (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The parallel decoder architecture supports throughputs up to 1 Gb/s and convergence in the decoding algorithm translates into extremely low switching activity with power dissipation under 220 mW.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"588","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2001.929780","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 588
Abstract
A 1024 bit rate-1/2 Low Density Parity Check (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The parallel decoder architecture supports throughputs up to 1 Gb/s and convergence in the decoding algorithm translates into extremely low switching activity with power dissipation under 220 mW.
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