Evaluation of tunnel FET-based flip-flop designs for low power, high performance applications

M. Cotter, Huichu Liu, S. Datta, N. Vijaykrishnan
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引用次数: 23

Abstract

As proliferation of embedded systems and mobile devices increases, power has become one of the most paramount concerns in current microprocessor designs. Technology scaling has provided many benefits in terms of dynamic power; however, static power has become the bottleneck to reducing power. We address this by evaluating Tunnel FETs (TFETs) for use in low-power, high-performance flip-flop designs. Due to the nature of TFETs, some of the flip-flop designs that are evaluated require additional modifications beyond simple device replacement-most notably the pseudo-static D flip-flop (DFF). We find that despite these additional transistors, the low voltage TFET DFF provides clear advantages in power and energy combined with performance comparable to higher voltage MOSFET and FinFET designs.
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基于隧道场效应晶体管的低功耗高性能触发器设计评估
随着嵌入式系统和移动设备的激增,功耗已成为当前微处理器设计中最重要的问题之一。技术扩展在动态功率方面提供了许多好处;然而,静电已成为降低功耗的瓶颈。我们通过评估隧道场效应管(tfet)在低功耗、高性能触发器设计中的应用来解决这个问题。由于tfet的性质,一些被评估的触发器设计需要额外的修改,而不是简单的器件更换-最明显的是伪静态D触发器(DFF)。我们发现,尽管有这些额外的晶体管,低压TFET DFF在功率和能量方面具有明显的优势,其性能可与高压MOSFET和FinFET设计相媲美。
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