Die level thermal storage for improved cooling of pulsed devices

Abstract

In many communications applications semiconductor devices operate in a pulsed mode, where rapid temperature transients are continuously experienced within the die. We proposed a novel junction-level cooling technology where a metallic phase change material (PCM) was embedded in close proximity to the active transistor channels without interfering with the device's electrical response. Here we present multiscale simulations that were performed to determine the thermal performance improvement and electrical performance impact under pulsed operating conditions. The modeling effort was focused on Gallium Nitride (GaN) on Silicon (Si) chips with Indium (In) as the PCM. To accurately capture the microscale transient melting process, a hierarchical multiscale model was developed that includes linking of atomistic-level molecular dynamics simulations and macroscale finite element analysis simulations. Macroscale physics, including the melting process, were captured with a transient two-dimensional finite element analysis (FEA) model. The FEA model also includes interfacial and contact resistances between the semiconductor materials and PCM. Non-equilibrium Molecular Dynamic (MD) simulations were performed to estimate the value of the interfacial resistances between the Si substrate and the In PCM, which included a new interatomic potential between In and Si that was developed from experimental scattering results available in the literature. The thermal modeling results indicate 26% more heat can be dissipated through the PCM enhanced transistor while maintain a safe operating temperature. A separate electrical modeling effort showed that the metallic PCM layer did not create appreciable parasitic capacitances as long as the PCM was farther than 1μm from the active channel. The lower, more constant temperatures achieved by this technology can help improve the reliability and performance of future communication devices.