Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767175
H. Wang, A. Mamishev
Future thermal management of microelectronics demands high heat flux removal capabilities due to rapid increases in component and heat flux densities generated from integrated circuits (ICs). Although electrospray evaporative cooling (ESEC) has been investigated as the potential package-level thermal management solution for future microelectronics, the optimal heat transfer performance of ESEC devices using a different number of nozzles has not been thoroughly investigated as a whole. This paper presents three different kinds of ESEC chambers with different spacing, in order to investigate their optimal heat transfer performances. The maximum enhancement ratio of 1.87 was achieved by the 8-nozzle 5 mm spacing ESEC chamber at the lowest heat flux. The optimal heat transfer performance for the 4-nozzle chamber is the chamber with 6 mm spacing. Both the 8-nozzle 5 mm spacing ESEC chamber and the 8-nozzle 6 mm spacing ESEC chamber achieve optimal heat transfer performance. Furthermore, although the increase in the number of electrospray nozzles of the ESEC chambers does not provide obvious improvement on the maximum achievable heat transfer enhancement ratio, the highest cooling rate is noticeably enhanced by increasing the number of electrospray nozzles of the ESEC chamber.
{"title":"Optimal heat transfer performance of the microfluidic electrospray cooling devices","authors":"H. Wang, A. Mamishev","doi":"10.1109/STHERM.2011.5767175","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767175","url":null,"abstract":"Future thermal management of microelectronics demands high heat flux removal capabilities due to rapid increases in component and heat flux densities generated from integrated circuits (ICs). Although electrospray evaporative cooling (ESEC) has been investigated as the potential package-level thermal management solution for future microelectronics, the optimal heat transfer performance of ESEC devices using a different number of nozzles has not been thoroughly investigated as a whole. This paper presents three different kinds of ESEC chambers with different spacing, in order to investigate their optimal heat transfer performances. The maximum enhancement ratio of 1.87 was achieved by the 8-nozzle 5 mm spacing ESEC chamber at the lowest heat flux. The optimal heat transfer performance for the 4-nozzle chamber is the chamber with 6 mm spacing. Both the 8-nozzle 5 mm spacing ESEC chamber and the 8-nozzle 6 mm spacing ESEC chamber achieve optimal heat transfer performance. Furthermore, although the increase in the number of electrospray nozzles of the ESEC chambers does not provide obvious improvement on the maximum achievable heat transfer enhancement ratio, the highest cooling rate is noticeably enhanced by increasing the number of electrospray nozzles of the ESEC chamber.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125337427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767204
D. Schweitzer, H. Pape, Liu Chen, R. Kutscherauer, Martin Walder
The junction-to-case thermal resistance Rth-JC is an important thermal characteristic for power semiconductor devices. Its value is often one of the main criteria for the decision whether a device can be used in a thermally demanding environment, and a low Rth-JC therefore is a competitive advantage for the semiconductor manufacturer. On the other hand the vendors must ensure that their data-sheet values do not underestimate the actual Rth-JC values. Hence accurate and reproducible methods to measure the Rth-JC are required. Unfortunately these requirements are not easy to meet, which is reflected by the fact that until very recently there existed no JEDEC industry standard for the determination of this thermal metric. During the last three years we have intensely tested and further developed a new transient measurement method for the Rth-JC of power semiconductor packages with a single heat flow path. The so called transient dual interface measurement (TDIM) which allows measuring the Rth-JC with higher accuracy and better reproducibility than traditional methods has now been accepted as JEDEC standard JESD51–14.
{"title":"Transient dual interface measurement — A new JEDEC standard for the measurement of the junction-to-case thermal resistance","authors":"D. Schweitzer, H. Pape, Liu Chen, R. Kutscherauer, Martin Walder","doi":"10.1109/STHERM.2011.5767204","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767204","url":null,"abstract":"The junction-to-case thermal resistance Rth-JC is an important thermal characteristic for power semiconductor devices. Its value is often one of the main criteria for the decision whether a device can be used in a thermally demanding environment, and a low Rth-JC therefore is a competitive advantage for the semiconductor manufacturer. On the other hand the vendors must ensure that their data-sheet values do not underestimate the actual Rth-JC values. Hence accurate and reproducible methods to measure the Rth-JC are required. Unfortunately these requirements are not easy to meet, which is reflected by the fact that until very recently there existed no JEDEC industry standard for the determination of this thermal metric. During the last three years we have intensely tested and further developed a new transient measurement method for the Rth-JC of power semiconductor packages with a single heat flow path. The so called transient dual interface measurement (TDIM) which allows measuring the Rth-JC with higher accuracy and better reproducibility than traditional methods has now been accepted as JEDEC standard JESD51–14.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130385418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767196
K. Fushinobu, T. Hatakeyama
Scaling issues in thermal behavior of silicon MOSFETs have been discussed for devices with typically larger than 100 nm. Cutting edge technologies of silicon devices are exploring the issues in deep nanometer length scales, where it is claimed that the conventional Fourier-based thermal model does not apply. It is also claimed that the BTE-based transport model is the theoretical tool to discuss the transport phenomena in sub-100 nm length scale to a certain extent of miniaturization. There however still exist unorganized thermal issues to be considered in over-100 nm regime. This research investigates the trend of thermal issues, mainly the lattice and carrier temperatures, based on the device scaling. Simple algebraic model of lattice and electron temperatures of bulk Si MOSFET is developed. Thermal behavior of the devices is discussed based on various scaling laws and actual trend. A Multi-fluid model, a full set of partial difference equations of continuum model and constitutive equations, is solved numerically to obtain the temperature distributions in the device. The results show clear threshold of the length scale where the temperature distribution and the hot spot, spatially local high temperature region, behavior changes drastically with miniaturization. Discussions show the characteristics of thermal scaling of bulk Si MOSFETs over 100 nm range.
{"title":"Thermal scaling consideration of Si MOSFETs with gate length typically larger than 100 nm","authors":"K. Fushinobu, T. Hatakeyama","doi":"10.1109/STHERM.2011.5767196","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767196","url":null,"abstract":"Scaling issues in thermal behavior of silicon MOSFETs have been discussed for devices with typically larger than 100 nm. Cutting edge technologies of silicon devices are exploring the issues in deep nanometer length scales, where it is claimed that the conventional Fourier-based thermal model does not apply. It is also claimed that the BTE-based transport model is the theoretical tool to discuss the transport phenomena in sub-100 nm length scale to a certain extent of miniaturization. There however still exist unorganized thermal issues to be considered in over-100 nm regime. This research investigates the trend of thermal issues, mainly the lattice and carrier temperatures, based on the device scaling. Simple algebraic model of lattice and electron temperatures of bulk Si MOSFET is developed. Thermal behavior of the devices is discussed based on various scaling laws and actual trend. A Multi-fluid model, a full set of partial difference equations of continuum model and constitutive equations, is solved numerically to obtain the temperature distributions in the device. The results show clear threshold of the length scale where the temperature distribution and the hot spot, spatially local high temperature region, behavior changes drastically with miniaturization. Discussions show the characteristics of thermal scaling of bulk Si MOSFETs over 100 nm range.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121954469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767188
T. Brunschwiler, S. Paredes, U. Drechsler, B. Michel, B. Wunderle, H. Reichl
Interlayer cooling removes the heat dissipated by vertically stacked chips in multiple integrated fluid cavities. Its performance scales with the number of dies in the stack and is therefore superior to traditional back-side heat removal. Previous work indicated that pin-fin arrays are ideally suited as through-silicon-via-compatible heat transfer structures. In addition, four-port fluid-delivery and fluid-guiding structures improve the heat-removal performance for the nonuniform power maps of high-performance microprocessor chip stacks. Accordingly, an extension of the porous-media multi-scale modeling approach is presented as an efficient approach for designing nonuniform heat transfer cavities. A tensor description in combination with a look-up table is proposed to physically describe periodic porous media, such as pin-fin arrays, in detail. Conjugate heat and mass transfer sub-domain modeling is performed with periodic boundary conditions to derive the orientation-dependent permeability and angle offset between the pressure gradient and the Darcy velocity direction for pin-fin arrays with a pin diameter of 50 μm and pitch and height of 100 μm. A local permeability minimum at a flow direction of approx. 30° could be identified. At higher velocities, the fluid flow is biased towards the symmetry lines of the pin-fin array. The modeling concept was validated with experimental readings of a nonuniform, double-side-heated single test cavity. The main characteristics of the temperature field with respect to the four-port architecture, the guiding structures, the fluid temperature increase, and the nonuniform power dissipation are predicted correctly. A statistical comparison of power maps with different heat transfer contrast values resulted in a mean accuracy <6% at a maximal standard deviation of 22.2%. Finally, the potential of the four-port architecture for nonuniform power maps with hot spots in the corners was demonstrated.
{"title":"Angle-of-attack investigation of pin-fin arrays in nonuniform heat-removal cavities for interlayer cooled chip stacks","authors":"T. Brunschwiler, S. Paredes, U. Drechsler, B. Michel, B. Wunderle, H. Reichl","doi":"10.1109/STHERM.2011.5767188","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767188","url":null,"abstract":"Interlayer cooling removes the heat dissipated by vertically stacked chips in multiple integrated fluid cavities. Its performance scales with the number of dies in the stack and is therefore superior to traditional back-side heat removal. Previous work indicated that pin-fin arrays are ideally suited as through-silicon-via-compatible heat transfer structures. In addition, four-port fluid-delivery and fluid-guiding structures improve the heat-removal performance for the nonuniform power maps of high-performance microprocessor chip stacks. Accordingly, an extension of the porous-media multi-scale modeling approach is presented as an efficient approach for designing nonuniform heat transfer cavities. A tensor description in combination with a look-up table is proposed to physically describe periodic porous media, such as pin-fin arrays, in detail. Conjugate heat and mass transfer sub-domain modeling is performed with periodic boundary conditions to derive the orientation-dependent permeability and angle offset between the pressure gradient and the Darcy velocity direction for pin-fin arrays with a pin diameter of 50 μm and pitch and height of 100 μm. A local permeability minimum at a flow direction of approx. 30° could be identified. At higher velocities, the fluid flow is biased towards the symmetry lines of the pin-fin array. The modeling concept was validated with experimental readings of a nonuniform, double-side-heated single test cavity. The main characteristics of the temperature field with respect to the four-port architecture, the guiding structures, the fluid temperature increase, and the nonuniform power dissipation are predicted correctly. A statistical comparison of power maps with different heat transfer contrast values resulted in a mean accuracy <6% at a maximal standard deviation of 22.2%. Finally, the potential of the four-port architecture for nonuniform power maps with hot spots in the corners was demonstrated.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117213699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767210
R. Mohammed, R. Sahan, Yi Xia, Y. Pang
Thermal tools provide temperature margining capability by varying the case temperature at silicon thermal design power (TDP). They are used for process, voltage, temperature and frequency (PVTF) testing by Intel's post-silicon validation customers across servers, desktops, mobile and graphics segments. Thermal margining tools are widely used in silicon debug validation by varying the case temperature over a wide operating range of specifications of the Silicon to i) validate the silicon, ii) accelerate fault detection, and iii) reduce escapes and identify bugs. Thermal tool is controlled by a thermal controller to provide a temperature set-point based on the device under test's (DUT's) case or junction diode temperature. Air cooled thermal tool (AC-TT) employs a controller card to achieve the margining capability by running the tool's thermoelectric cooler (TEC), a Peltier device, within the optimal temperature range. AC-TT has an active heat sink design to remove the heat dissipated by the TEC and the silicon. Although AC-TT is expected to provide narrower range of margining capability due to the limitations of air cooling, they still can be an excellent solution for some specific thermal margining applications. Therefore, a new line of AC-TTs were developed for validation customers whose needs can be addressed without requiring costly controllers and noisy chillers while enhancing the user-experience. This paper presents the design improvement strategies implemented for developing the new line of CPU, Chipset and ASIC AC-TTs. Improved designs provide wider margining capability by using i) high performance active heat sink designs, ii) high power thermo-electric cooler (TEC), iii) cold plate designs compatible to keep out volume (KOV), iv) new choice of thermal interface material (TIM), and v) new retention design. This paper discusses the details of the design process and how multiple design strategies are implemented to finalize the design and to achieve the overall performance improvement while keeping the cost of the AC-TT low. The new line of AC-TT designs have performance improvement of 44% (∼25C) for 130W CPU TT compared to existing CPU AC-TT, of 32% (∼19C) for 60W chipset compared to existing chipset AC-TT, and of 41% (∼8C) compared to existing 15W PCH (Peripheral Component Hub) AC-TT. Design strategies provided here can be easily adapted to develop future generation of low-cost CPU, chipset, and ASIC AC-TTs with a wider margining capability.
热工具通过在硅热设计功率(TDP)下改变外壳温度来提供温度边际能力。它们被英特尔的后硅验证客户用于服务器、台式机、移动设备和图形领域的工艺、电压、温度和频率(PVTF)测试。热边际工具广泛用于硅调试验证，通过在硅规格的广泛操作范围内改变外壳温度来i)验证硅，ii)加速故障检测，以及iii)减少逃逸和识别错误。热工具由热控制器控制，根据被测器件(DUT)的外壳或结二极管温度提供温度设定点。风冷式热工具(AC-TT)采用控制卡，通过在最佳温度范围内运行工具的热电冷却器(TEC) (Peltier设备)来实现余量能力。AC-TT具有主动散热器设计，以消除TEC和硅散发的热量。尽管由于空气冷却的限制，AC-TT预计将提供更窄范围的边际能力，但它们仍然可以成为一些特定热边际应用的出色解决方案。因此，为验证客户开发了新的交流- tt系列，这些客户的需求可以在不需要昂贵的控制器和嘈杂的冷却器的情况下得到满足，同时增强用户体验。本文介绍了为开发新的CPU、芯片组和ASIC ac - tt系列而实施的设计改进策略。改进的设计通过使用i)高性能主动散热器设计，ii)大功率热电冷却器(TEC)， iii)兼容的冷板设计来保持体积(KOV)， iv)热界面材料(TIM)的新选择，以及v)新的保留设计，提供更广泛的余量能力。本文讨论了设计过程的细节，以及如何实施多种设计策略来完成设计并实现整体性能改进，同时保持AC-TT的低成本。与现有的CPU AC-TT相比，130W CPU TT的性能提高了44% (~ 25C)， 60W芯片组与现有的芯片组AC-TT相比，性能提高了32% (~ 19C)，与现有的15W PCH(外围组件集线器)AC-TT相比，性能提高了41% (~ 8C)。这里提供的设计策略可以很容易地用于开发下一代低成本CPU、芯片组和具有更广泛边际能力的ASIC ac - tt。
{"title":"High performance air-cooled temperature margining thermal tools for silicon validation","authors":"R. Mohammed, R. Sahan, Yi Xia, Y. Pang","doi":"10.1109/STHERM.2011.5767210","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767210","url":null,"abstract":"Thermal tools provide temperature margining capability by varying the case temperature at silicon thermal design power (TDP). They are used for process, voltage, temperature and frequency (PVTF) testing by Intel's post-silicon validation customers across servers, desktops, mobile and graphics segments. Thermal margining tools are widely used in silicon debug validation by varying the case temperature over a wide operating range of specifications of the Silicon to i) validate the silicon, ii) accelerate fault detection, and iii) reduce escapes and identify bugs. Thermal tool is controlled by a thermal controller to provide a temperature set-point based on the device under test's (DUT's) case or junction diode temperature. Air cooled thermal tool (AC-TT) employs a controller card to achieve the margining capability by running the tool's thermoelectric cooler (TEC), a Peltier device, within the optimal temperature range. AC-TT has an active heat sink design to remove the heat dissipated by the TEC and the silicon. Although AC-TT is expected to provide narrower range of margining capability due to the limitations of air cooling, they still can be an excellent solution for some specific thermal margining applications. Therefore, a new line of AC-TTs were developed for validation customers whose needs can be addressed without requiring costly controllers and noisy chillers while enhancing the user-experience. This paper presents the design improvement strategies implemented for developing the new line of CPU, Chipset and ASIC AC-TTs. Improved designs provide wider margining capability by using i) high performance active heat sink designs, ii) high power thermo-electric cooler (TEC), iii) cold plate designs compatible to keep out volume (KOV), iv) new choice of thermal interface material (TIM), and v) new retention design. This paper discusses the details of the design process and how multiple design strategies are implemented to finalize the design and to achieve the overall performance improvement while keeping the cost of the AC-TT low. The new line of AC-TT designs have performance improvement of 44% (∼25C) for 130W CPU TT compared to existing CPU AC-TT, of 32% (∼19C) for 60W chipset compared to existing chipset AC-TT, and of 41% (∼8C) compared to existing 15W PCH (Peripheral Component Hub) AC-TT. Design strategies provided here can be easily adapted to develop future generation of low-cost CPU, chipset, and ASIC AC-TTs with a wider margining capability.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130579703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767218
A. Vass-Várnai, V. Székely, Z. Sárkány, M. Rencz
The thermal management of semiconductor devices and systems has become a widely discussed topic over the past decades due to the ever increasing integration and the resulting power densities inside the packages. The increasing junction temperature is a great threat for the operation and the long-term reliability of the packaged device. One of the most important barriers in the heat conduction path is the thermal interface material. Their thermal performance significantly influences the overall thermal resistance of a system from the junction to the ambient. In this paper two approaches are described for the accurate thermal conductivity measurement of these materials; both techniques were developed in the framework of the European Nanopack project. One of them is a highly accurate, scientific method which benefits from the improvements of the semiconductor industry: the TIM is measured between two bare sensor chip surfaces. The other method is based on thermal transient testing and allows the measurement of a given grease or paste in its real environment. Both of them are capable of the measurement of highly conductive, nanoparticle based TIM materials. In this paper these two methods are explained in more details and measured results are compared with each-other. The effect of the measurement arrangement on the measured thermal resistance values is also discussed.
{"title":"New level of accuracy in TIM measurements","authors":"A. Vass-Várnai, V. Székely, Z. Sárkány, M. Rencz","doi":"10.1109/STHERM.2011.5767218","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767218","url":null,"abstract":"The thermal management of semiconductor devices and systems has become a widely discussed topic over the past decades due to the ever increasing integration and the resulting power densities inside the packages. The increasing junction temperature is a great threat for the operation and the long-term reliability of the packaged device. One of the most important barriers in the heat conduction path is the thermal interface material. Their thermal performance significantly influences the overall thermal resistance of a system from the junction to the ambient. In this paper two approaches are described for the accurate thermal conductivity measurement of these materials; both techniques were developed in the framework of the European Nanopack project. One of them is a highly accurate, scientific method which benefits from the improvements of the semiconductor industry: the TIM is measured between two bare sensor chip surfaces. The other method is based on thermal transient testing and allows the measurement of a given grease or paste in its real environment. Both of them are capable of the measurement of highly conductive, nanoparticle based TIM materials. In this paper these two methods are explained in more details and measured results are compared with each-other. The effect of the measurement arrangement on the measured thermal resistance values is also discussed.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122404842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767209
D. Saums
Liquid cooling concepts for power electronics applications have historically used single-phase water/glycol mixtures or deionized water as a primary coolant. Engineered dielectric liquids such as perfluorinated fluorocarbons and fluoroketones are also used, especially in power semiconductor applications for traction and for semiconductor testing, relying on sensible heat transport via a single-phase mechanically pumped loop. Common dielectric fluids such as refrigerants used as coolants in mechanically-pumped two-phase systems have recently been commercialized for cooling IGBT semiconductors in power electronics. Comparative performance data is described. Advanced cooling systems can impact power semiconductor performance, electronic system cost, system volume, and electrical architecture.
{"title":"Applications of vaporizable dielectric fluid cooling for IGBT power semiconductors","authors":"D. Saums","doi":"10.1109/STHERM.2011.5767209","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767209","url":null,"abstract":"Liquid cooling concepts for power electronics applications have historically used single-phase water/glycol mixtures or deionized water as a primary coolant. Engineered dielectric liquids such as perfluorinated fluorocarbons and fluoroketones are also used, especially in power semiconductor applications for traction and for semiconductor testing, relying on sensible heat transport via a single-phase mechanically pumped loop. Common dielectric fluids such as refrigerants used as coolants in mechanically-pumped two-phase systems have recently been commercialized for cooling IGBT semiconductors in power electronics. Comparative performance data is described. Advanced cooling systems can impact power semiconductor performance, electronic system cost, system volume, and electrical architecture.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130188048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767177
L. Campbell, R. Wagner, R. Simons
A thermoelectric chiller is a potential replacement for sub-ambient refrigeration for electronics cooling applications, where the reliance on vapor compression refrigeration results in risk of cooling failure due to the mechanical nature of the compressor and electronic expansion valve. Another benefit of a thermoelectric chiller is that controllable cooling of the electronic component can be achieved regardless of ambient conditions, and the ultimate heat sink can be either air or facility water. The goal of the work described herein is to study a thermoelectric chiller with reasonable capacity (in Watts), coefficient of performance (COP), and reliability (mean time between failures, MTBF), for electronics cooling applications. Four sets of tests are presented: a thermoelectric module tested with a heater block and a cold plate (Figure 2), and thermoelectric heat exchanger tests where the thermoelectric module hot and cold sides are arranged in segregated loops (Figure 5), a single serial loop (Figure 6), and parallel loops (Figure 7).
{"title":"Analysis and characterization of thermoelectric module and heat exchanger performance in a hybrid system cooling application","authors":"L. Campbell, R. Wagner, R. Simons","doi":"10.1109/STHERM.2011.5767177","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767177","url":null,"abstract":"A thermoelectric chiller is a potential replacement for sub-ambient refrigeration for electronics cooling applications, where the reliance on vapor compression refrigeration results in risk of cooling failure due to the mechanical nature of the compressor and electronic expansion valve. Another benefit of a thermoelectric chiller is that controllable cooling of the electronic component can be achieved regardless of ambient conditions, and the ultimate heat sink can be either air or facility water. The goal of the work described herein is to study a thermoelectric chiller with reasonable capacity (in Watts), coefficient of performance (COP), and reliability (mean time between failures, MTBF), for electronics cooling applications. Four sets of tests are presented: a thermoelectric module tested with a heater block and a cold plate (Figure 2), and thermoelectric heat exchanger tests where the thermoelectric module hot and cold sides are arranged in segregated loops (Figure 5), a single serial loop (Figure 6), and parallel loops (Figure 7).","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116719144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767203
S. Ankireddi
Current generations of high performance microprocessors feature multiple cores and micro-cores, with each supporting multiple threads implemented in hardware. Such designs routinely feature billions of transistors, and chip layout teams are frequently hard pressed for placement and routing of all the functional blocks and sub-blocks that go into the design. An additional complexity arises because system engineers would like to have each micro-cores temperature monitored for silicon reliability and system performance reasons, which translates into them requiring that each core preferably be outfitted with a thermal sensor that routed out to the external world. Since die real estate is already at a premium and sensor macros can often be large, CPU design teams frequently shy away from placing and routing one sensor per each micro-core. The practical implication of this is that there is no means to monitor how hot any given micro-core is getting during field operation — which can compound risk significantly from the standpoints of silicon reliability (GoX, TDDB), chip electrical performance (timing, clock skew, jitter) and system performance (real time benchmarks, field performance, data coherency etc). In this study, a multi-core processor chip with a wide range of core-to-core power variability is considered. A finite number of sensor locations, which are known to be thermally sub-optimal, are assumed to be available for placement and routing. Using sensory data from these “poor” locations and an offline training algorithm, temperatures of all key core locations are determined using a causal, linear least-squares error basis. The resulting formulation is tested for prediction integrity using a large sample Monte Carlo analysis, and the temperature predictions are found to be robust. The technique developed is general enough to be applied across any microprocessor product family. The study concludes with suggested techniques to maintain prediction robustness in the presence of measurement errors, diode part-to-part variation and other inaccuracies. The approach proposed here can circumvent the limitations on placing and routing multiple diodes in real-estate constrained multi-core microprocessor and ASIC applications.
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Pub Date : 2011-03-20DOI: 10.1109/STHERM.2011.5767192
S. M. Kwark, Miguel Amaya, S. M. You
An experimental pool boiling study was conducted using plain and nanocoated heater surfaces immersed in various working fluids. Working fluids include water, ethanol and HFE-7100 and pool boiling tests were performed on a flat 1 cm × 1 cm heaters. Unlike in water, CHF enhancement of the nanocoating seems to be less or marginal in ethanol and HFE-7100 at 1 atm. The reduced effect of the nanocoating in ethanol and HFE-7100 is believed to be due to the highly wetting nature of these fluids since no obvious difference in wettability through apparent contact angle measurement is observed between nanocoated and uncoated surfaces at 1 atm. Moreover, pressure effects were also investigated for the fluids mentioned above. The uncoated and nanocoated surfaces were tested in the working fluids at four different pressures. For the uncoated surface, measured CHF values closely matched those of Zuber's [13]. In the case of the nanocoated surface, CHF enhancement of the nanocoating appeared to be dependent on the test pressure, showing the greatest CHF enhancement value at the lowest pressure and the enhancement decreased as the pressure increased. Although CHF enhancement of pure water was superior to that of other fluids, it was observed that there was also noticeable CHF enhancement as pressure decreased for the highly wetting fluids. It is believed that this enhancement could be closely related to the bubble departure diameter. As the test pressure decreases, the departure bubble size increases and this allows the nanocoating to become more influential, even for the highly wetting fluids, in delaying local dry-out, which in turn results in increasing CHF enhancement.
{"title":"Pool boiling heat transfer characteristics of nanocoating in various working fluids","authors":"S. M. Kwark, Miguel Amaya, S. M. You","doi":"10.1109/STHERM.2011.5767192","DOIUrl":"https://doi.org/10.1109/STHERM.2011.5767192","url":null,"abstract":"An experimental pool boiling study was conducted using plain and nanocoated heater surfaces immersed in various working fluids. Working fluids include water, ethanol and HFE-7100 and pool boiling tests were performed on a flat 1 cm × 1 cm heaters. Unlike in water, CHF enhancement of the nanocoating seems to be less or marginal in ethanol and HFE-7100 at 1 atm. The reduced effect of the nanocoating in ethanol and HFE-7100 is believed to be due to the highly wetting nature of these fluids since no obvious difference in wettability through apparent contact angle measurement is observed between nanocoated and uncoated surfaces at 1 atm. Moreover, pressure effects were also investigated for the fluids mentioned above. The uncoated and nanocoated surfaces were tested in the working fluids at four different pressures. For the uncoated surface, measured CHF values closely matched those of Zuber's [13]. In the case of the nanocoated surface, CHF enhancement of the nanocoating appeared to be dependent on the test pressure, showing the greatest CHF enhancement value at the lowest pressure and the enhancement decreased as the pressure increased. Although CHF enhancement of pure water was superior to that of other fluids, it was observed that there was also noticeable CHF enhancement as pressure decreased for the highly wetting fluids. It is believed that this enhancement could be closely related to the bubble departure diameter. As the test pressure decreases, the departure bubble size increases and this allows the nanocoating to become more influential, even for the highly wetting fluids, in delaying local dry-out, which in turn results in increasing CHF enhancement.","PeriodicalId":128077,"journal":{"name":"2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124516936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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