Design and modeling challenges for DDR II memory subsystems

Abstract

This paper describes the electrical packaging challenges, design issues, and design solutions for source-synchronous DDR II memory subsystems utilizing the double data rate (DDR) timing protocols. Major design and modeling issues are discussed, such as crosstalk, delay skew, impedance control and inter-symbol interference. The timing and jitter budgets, and the noise margin allocation for the various components of the optimization equations are discussed in conjunction with their associated design control techniques. A novel termination technique is discussed that allows for maximum memory capacity per channel at a given data rate.