Device scaling in COSMOS architecture

Abstract

The Si nanoelectronic engineering have recently reached a level of capability, which make 3D processing and strain engineering on silicon-on-insulator (SOI) substrates not only possible [1,2], but also a necessity in order to surmount practical limitations of conventional planar CMOS [3]. Thus, device designers are presented with a multitude of options in exploring new designs, as evident in the proliferation of alternative architectures, including multi-gated, strained Si/SiGe channel, Schottky and Tunneling MOSFETs. While these structures have unique features superior to conventional bulk devices, nonetheless, they still retain the redundancy inherent to CMOS operation, namely building two devices even though only one operates at a given stable output. In this paper we demonstrate and design, through the use of 1/2/3D device simulations, a novel symmetrically operating CMOS device pair with a single gate structure having a unique device layout and ultra-thin strained channels [4]. The new architecture, named complementary orthogonal stacked MOS (COSMOS), places the n and pMOSFETs perpendicular to one another under a single gate, integrating them vertically (see Figs.1&2). Thus COSMOS can eliminate the aforementioned redundancy in CMOS and may result in dramatic savings (>50%) not only in active device area of a conventional digital CMOS layout, but also in R-C device parasitics associated with building and wiring two sets of devices for a single Boolean output function. We argue that the COSMOS structure is a natural candidate for very dense, low-power circuitry required in sub-5Onm scale. The proposed COSMOS architecture relies for operation on a conventional silicon electron channel grown atop a strained-SiGe channel for holes, as shown in Fig.2. To facilitate threshold tuning, reduce parallel conduction and eliminate need for doping, Ge concentration in the strained channel must be high. In accordance, the gate material may be a mid-gap metal, poly-SiGe alloy or polySi, depending on the choice of Ge concentration or background doping. The channel layers must be grown [5] or bonded [6] on a SOI substrate to allow isolation of both MOSFETs, while also keeping with the general scaling trends associated with low-leakage and low-parasitic SOI substrates. For a sample layer structure with a 4nm strained-Si03Ge0.7 hole channel and 3nm Si electron channel under a mid-gap metal gate, ID self-consistent Poisson-Schrodinger simulations (see Fig.3) indicate that symmetric population of both channels is possible with a threshold of IVTI=0.4±0.2 V. We also find that there is no significant parallel conduction in this layer structure, removing concerns for isolation in the stacked channels. Even for this non-optimum layer example, the carriers in both channels of COSMOS layers are well confined and have quite similar distributions. The use of large Ge concentration in the buried strained channel should improve hole mobility considerably over that of electrons in Si inversion channel. Thus, for x.0.3, hole mobility in strained Sii-.Gex layers should be comparable to or larger than electron mobility in undoped Si inversion layer [7]. By aligning p-MOSFET along the [011] direction [8], hole mobility may be further improved, thus restoring p-MOSFET transconductance deficit due to larger separation from the gate. In COSMOS, there are several independent parameters of layer structure, including layer composition, thickness and order, which can be used to optimize a symmetric device threshold. In Fig.4, we demonstrate how these parameters can be independently tailored to prevent parallel conduction and to set VT accurately. 3D TCAD simulations of the individual MOSFET characteristics (Fig.5) validate the ID analysis above, providing further support for the ability of symmetric control of two channels with a single gate. To show the usefulness of COSMOS for digital circuits, we simulated in 3D the transient response of a 40nm COSMOS NOT gate to an input pulse (Fig.6). The gate has respectable delay (lO00ps) and noise margin figures at low drive voltages (VDD+IVssl< .OV) used in sub-SOnm scale. These results illustrate the unique potential of COSMOS logic for low-power and high-density applications, which can be further enhanced by optimizing the structure and choice of symmetric VT. The delay of the gate can be improved at the expense of static leakage (Fig.7) due to parasitic p-i-n device turning on at highdrive conditions. To inhibit this, two additional etching steps are required during the fabrication of COSMOS structure [4]. Furthermore, the COSMOS gates have peculiar scaling trends, with smaller gate lengths having larger thresholds and smaller ON current below 20nm nodes due to reciprocal dependency of gate length and width in orthogonal device layout (Fig.8). The present study is an attempt at presenting how the novel COSMOS architecture can be operated, optimized and utilized in sub-50nm. We illustrate the design principles of this so far unexplored COSMOS architecture for optimum leakage and switching performance. This work shows how significant area and performance gains can be obtained in CMOS logic circuits by a unique combination of layout and channel engineering,