Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs

Shyue-Kung Lu, Shu-Ling Lin, Hao Lin, M. Hashizume
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Abstract

Hybrid scrambling technique is proposed for NROM-based ROMs in order to enhance the fabrication yield and reliability. Besides the traditional hardware redundancy techniques, fault masking features are also exploited to further improve the fabrication yield and reduce the amount of extra spare rows/columns. The hybrid scrambling technique basically consists of the row scrambling and the column scrambling techniques. Therefore, instead of scrambling a memory row/column, a logical memory cell can be scrambled into any of the logical memory cell address. This greatly improves the flexibility of scrambling. A hybrid scrambling control word is used for the control of the scrambling. Since the codes to be programmed into the NROM chips are known before programming, selecting a suitable code for programming a faulty NROM chip is helpful to further mask the faulty effects. Based on the proposed technique, possibilities of fault masking can be maximized. The proposed test and repair techniques can be easily incorporated into the ROM BIST architectures. According to experimental results, the fabrication yield can be improved significantly. Moreover, the incurred hardware overhead is almost negligible.
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提高基于nrom的rom制造成良率的混合置乱技术
为了提高nrom存储的成品率和可靠性,提出了基于nrom存储的混合置乱技术。除了传统的硬件冗余技术外,还利用故障屏蔽特性进一步提高了制作成品率,减少了多余的备用行/列的数量。混合置乱技术主要包括行置乱技术和列置乱技术。因此,可以将逻辑内存单元搅乱到任何逻辑内存单元地址中,而不是打乱内存行/列。这大大提高了置乱的灵活性。混合置乱控制字用于置乱控制。由于要编程到NROM芯片的代码在编程之前是已知的,因此选择合适的代码来编程有故障的NROM芯片有助于进一步掩盖故障的影响。基于该技术,可以最大限度地提高故障掩蔽的可能性。所提出的测试和修复技术可以很容易地集成到ROM BIST体系结构中。实验结果表明,该方法可显著提高加工成品率。此外,产生的硬件开销几乎可以忽略不计。
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