Incremental routing in FPGAs

Abstract

In this paper we present algorithms for incrementally routing circuits mapped to field-programmable gate arrays (FPGAs). The algorithms work well for ripping up and rerouting nets connected to small numbers of displaced logic blocks. Additionally the algorithms are sequential and compact, therefore making them ideal for embedding in hardware. Given an FPGA with a readable as well as writable configuration memory, these algorithms require no prior knowledge of the mapped circuit's netlist. Experimental results indicate our router works well for fault tolerance and other applications.