H. Hayashi, V. Axelrad, M. Mochizuki, T. Hayashi, T. Maruyama, Kazuya Suzuki, Y. Nagatomo
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Abstract
This paper presents the optimization of the two bit flash memory P-channel cell structure using efficient 2D write and erase model. Our proposed cell structure stores charge at either Source and/or Drain sides of the gate in an SiN film and is based on method of programming by DAHE and erasing by FN tunneling. It is found that expansion of cell window and the improvement of erase characteristic depend on the optimization of the gate-film overlap under gate of the SiN film.
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