A 27-mW 3.6-Gb/s I/O transceiver

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221173

K.L. Wong, M. Mansuri, H. Hatamkhani, C. Yang

引用次数: 48

Abstract

This paper describes a 3.6-Gbps 27-mW transceiver for chip-to-chip applications. A novel data receiving and timing recovery technique are presented with very low power penalties while maintaining high signal integrity. The input comparator filters noise with built-in bandwidth control and digital offset compensation while consuming 300 uW. Static phase offset introduced onto the charge-pump permits phase recovery with no additional power. The entire design occupies 0.2 mm/sup 2/ in a 0.18-/spl mu/m 1.8-V CMOS technology.

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一个27mw的3.6 gb /s I/O收发器

本文介绍了一种用于片对片应用的3.6 gbps 27mw收发器。提出了一种新的数据接收和定时恢复技术，在保持高信号完整性的同时，功耗损失很小。输入比较器通过内置带宽控制和数字偏移补偿过滤噪声，同时消耗300 uW。引入电荷泵的静态相位偏移允许相位恢复，而不需要额外的功率。整个设计占地0.2 mm/sup / /，采用0.18-/spl mu/m的1.8 v CMOS技术。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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