{"title":"Merged current mode logic","authors":"P. Zdebel, W. Engl","doi":"10.1109/ISSCC.1984.1156657","DOIUrl":null,"url":null,"abstract":"The use of down and up transistors to form nonsaturating and merged current mode logic resulting in a power-delay product of 0.1pJ for power dissipation less than 50μW/gate and a minimum delay of 1.6ns at 200μW/gate will be described.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XXVII 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1984.1156657","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
The use of down and up transistors to form nonsaturating and merged current mode logic resulting in a power-delay product of 0.1pJ for power dissipation less than 50μW/gate and a minimum delay of 1.6ns at 200μW/gate will be described.
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