{"title":"Path delay testing: variable-clock versus rated-clock","authors":"S. Majumder, M. Bushnell, V. Agrawal","doi":"10.1109/ICVD.1998.646651","DOIUrl":null,"url":null,"abstract":"There are two methods for applying path delay tests to a sequential circuit. We show that all path delay faults that can affect the rated-clock operation of the circuit are testable by the variable-clock method. Also, all path delay faults that are untestable by the variable-clock method are, in fact, untestable by the rated-clock method. However, some faults tested by the variable-clock method may be incapable of affecting the rated-clock operation. Our study is based on a finite-state machine model in which fault-free transitions are shown by green arcs. Faulty transitions are shown by red arcs. A test traverses successive arcs until a faulty output occurs. A variable-clock test can exercise more flexibility in selecting from green and red arcs. It can cover all functional paths, but may find only a proper subset of untestable paths. Our analysis assumes a delay fault, consisting of either a singly-testable path or multiply-testable paths, and hence corresponds to non-robust detection.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"70 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Eleventh International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVD.1998.646651","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
Abstract
There are two methods for applying path delay tests to a sequential circuit. We show that all path delay faults that can affect the rated-clock operation of the circuit are testable by the variable-clock method. Also, all path delay faults that are untestable by the variable-clock method are, in fact, untestable by the rated-clock method. However, some faults tested by the variable-clock method may be incapable of affecting the rated-clock operation. Our study is based on a finite-state machine model in which fault-free transitions are shown by green arcs. Faulty transitions are shown by red arcs. A test traverses successive arcs until a faulty output occurs. A variable-clock test can exercise more flexibility in selecting from green and red arcs. It can cover all functional paths, but may find only a proper subset of untestable paths. Our analysis assumes a delay fault, consisting of either a singly-testable path or multiply-testable paths, and hence corresponds to non-robust detection.