Defect Characterization and Test Generation for Spintronic-based Compute-In-Memory

Abstract

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), as one of the most promising emerging memory technology for on-chip memory, offers many advantageous features such as high density, non-volatility, scalability, high endurance and CMOS compatibility. Additionally, its resistive storage concept can be utilized for Compute-in-Memory (CiM), where bit-wise logical operations can be performed within the memory without the need for transferring the data from the memory to the processor and back. However, these new CiM operations are impacted by defects, resulting in faults which are different from the conventional memory faults. Hence, these CiM specific faults need to be modeled and appropriate test strategies need to be derived to ensure correct functionality of the CiM enabled memories. In this paper, we first perform extensive defect injection in the CiM bit-cell and build fault models based on the impact of the defects. We also compare CiM specific faults to normal memory faults based on this technology. From this model, we derive an efficient test algorithm to fully cover CiM related faults, which cannot be found with conventional memory test algorithms.