A platform-based highly parallel digital signal processor

Abstract

Realizations of demanding applications particularly in the field of mobile communications often require processing performance which is far beyond what is delivered by DSPs today. To avoid designing inflexible ASIC solutions a powerful, highly parallel DSP core for System-on-Chip domains is presented in this paper. Targeted for a wireless OFDM based modem application the fixed-point DSP core consists of 16/spl times/16-bit datapath units in parallel providing 640 M MAC operations per second. In a Galois field split mode 32 8-bit datapaths deliver 1.28 G MAC/s. The DSP is based on a scalable architecture which supports customization depending on the application needs. The 289 mm/sup 2/ chip was manufactured in a 0.35 /spl mu/m CMOS technology, operates at 40 MHz and dissipates <1 W from a 3.3 V supply. This low power approach outperforms commercial DSPs running at 200 MHz.