Junho Lee, Hyunseok Kim, Kimyung Kyung, Minyoung You, Hyungdong Lee, Kunwoo Park, Byong-Tae Chung
{"title":"Design, Analysis, and Optimization of DDR2 Memory Power Delivery Network","authors":"Junho Lee, Hyunseok Kim, Kimyung Kyung, Minyoung You, Hyungdong Lee, Kunwoo Park, Byong-Tae Chung","doi":"10.1109/EPEP.2007.4387131","DOIUrl":null,"url":null,"abstract":"In this paper, design procedure and analysis method of power delivery network of DDR2 memory chip are introduced. The power delivery network of memory chip is optimized by tuning the location of power/ground chip pad and on-chip decoupling capacitor's W/L size. The results show that the properly designed power/ground chip pads and decoupling capacitors greatly reduce power noise, resulting in the reduction of chip cost by using less area for on-chip decoupling capacitor.","PeriodicalId":402571,"journal":{"name":"2007 IEEE Electrical Performance of Electronic Packaging","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Electrical Performance of Electronic Packaging","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.2007.4387131","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In this paper, design procedure and analysis method of power delivery network of DDR2 memory chip are introduced. The power delivery network of memory chip is optimized by tuning the location of power/ground chip pad and on-chip decoupling capacitor's W/L size. The results show that the properly designed power/ground chip pads and decoupling capacitors greatly reduce power noise, resulting in the reduction of chip cost by using less area for on-chip decoupling capacitor.
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