{"title":"A 250 Msample/sec programmable cascaded integrator-comb decimation filter","authors":"A. Kwentus, O. Lee, A. Willson","doi":"10.1109/VLSISP.1996.558351","DOIUrl":null,"url":null,"abstract":"The implementation of a 250 Msample/sec programmable six-stage cascaded integrator-comb (CIC) decimation filter is described. The prototype IC is implemented using 0.8-/spl mu/m CMOS and contains 39,890 transistors in a core area of 8.5 mm/sup 2/. It accommodates programmable power-of-two decimation factors from 2 to 1024 with 16-bit input and output data.","PeriodicalId":290885,"journal":{"name":"VLSI Signal Processing, IX","volume":"67 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI Signal Processing, IX","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSISP.1996.558351","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 20
Abstract
The implementation of a 250 Msample/sec programmable six-stage cascaded integrator-comb (CIC) decimation filter is described. The prototype IC is implemented using 0.8-/spl mu/m CMOS and contains 39,890 transistors in a core area of 8.5 mm/sup 2/. It accommodates programmable power-of-two decimation factors from 2 to 1024 with 16-bit input and output data.
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