Plenary Speech 2P2: Statistical Techniques to Achieve Robustness and Quality

Abstract

Summary form only given. Variability due to manufacturing, environmental and aging uncertainties constitutes one of the major challenges in continuing CMOS scaling. Worst-case design is simply not feasible any more.This presentation will describe how statistical timing techniques can be used to reduce pessimism, achieve full-chip and full-process coverage, and enable robust design practices. A practical ASIC methodology based on statistical timing will be described. Robust optimization techniques will be discussed. Variability makes post-manufacturing testing a daunting task. Process coverage is a new metric that must be considered. Statistical techniques to improve quality in the context of at-speed test will be presented. Key research initiatives required to achieve elements of a statistical design flow will be described.