Verification of Acceptance Filter Module Design based on UVM

Abstract

The increasing functional requirements of IC circuits make the verification stimulus complexity exponentially increasing, so the SystemVerilog language based UVM general verification methodology is gradually becoming the main verification method. The verification methodology based on SystemVerilog language UVM with verification methodology is used to design and verify the acceptance filtering module of CAN. The verification platform uses SystemVerilog to generate the UVM framework structure using Python automation scripts, combined with constrainable random testing techniques to write multiple test cases for functional points. The verification simulation results show that the verification coverage reaches 100%. In addition, the verification platform is easy to migrate, which can greatly improve the verification efficiency and shorten the verification time.