CGS(D)/CS(D)GCapacitance Phenomenon of 100nm Fully-Depleted SOI CMOS Devices with HfO2High-K Gate Dielectric Considering Vertical and Fringing Displacement Effects

2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI:10.1109/EDSSC.2005.1635214
Yu-Sheng Lin, Chia‐Hong Lin, J. Kuo, K. Su
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引用次数: 0

Abstract

This paper reports the CGS(D)/CS(D)Gcapacitance phenomenon of 100nm fully-depleted (FD) SOI CMOS devices with HfO2high-k gate dielectric considering vertical and fringing displacement effect. According to the 2D simulation results, a unique two-step CS(D)G/CGSversus VGcurve exists for the device with the 1.5nm HfO2gate dielectric due to the vertical and fringing displacement effects.
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考虑垂直位移和边缘位移效应的HfO2High-K栅极介质100nm满耗尽SOI CMOS器件CGS(D)/CS(D) g电容现象
本文报道了考虑垂直位移效应和边缘位移效应的hfo2高k栅极介质的100nm满耗尽(FD) SOI CMOS器件的CGS(D)/CS(D) g电容现象。二维仿真结果表明，由于垂直位移和边缘位移效应，1.5nm hfo2栅极介质器件存在独特的两步CS(D)G/ cgsvs . vg曲线。
本文章由计算机程序翻译，如有差异，请以英文原文为准。
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2005 IEEE Conference on Electron Devices and Solid-State Circuits
2005 IEEE Conference on Electron Devices and Solid-State Circuits
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