{"title":"The Law of Attraction: Affinity-Aware Placement Optimization using Graph Neural Networks","authors":"Yi-Chen Lu, S. Pentapati, S. Lim","doi":"10.1145/3439706.3447045","DOIUrl":null,"url":null,"abstract":"Placement is one of the most crucial problems in modern Electronic Design Automation (EDA) flows, where the solution quality is mainly dominated by on-chip interconnects. To achieve target closures, designers often perform multiple placement iterations to optimize key metrics such as wirelength and timing, which is highly time-consuming and computationally inefficient. To overcome this issue, in this paper, we present a graph learning-based framework named PL-GNN that provides placement guidance for commercial placers by generating cell clusters based on logical affinity and manually defined attributes of design instances. With the clustering information as a soft placement constraint, commercial tools will strive to place design instances in a common group together during global and detailed placements. Experimental results on commercial multi-core CPU designs demonstrate that our framework improves the default placement flow of Synopsys IC Compiler II (ICC2) by 3.9% in wirelength, 2.8% in power, and 85.7% in performance.","PeriodicalId":184050,"journal":{"name":"Proceedings of the 2021 International Symposium on Physical Design","volume":"56 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2021 International Symposium on Physical Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/3439706.3447045","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 19
Abstract
Placement is one of the most crucial problems in modern Electronic Design Automation (EDA) flows, where the solution quality is mainly dominated by on-chip interconnects. To achieve target closures, designers often perform multiple placement iterations to optimize key metrics such as wirelength and timing, which is highly time-consuming and computationally inefficient. To overcome this issue, in this paper, we present a graph learning-based framework named PL-GNN that provides placement guidance for commercial placers by generating cell clusters based on logical affinity and manually defined attributes of design instances. With the clustering information as a soft placement constraint, commercial tools will strive to place design instances in a common group together during global and detailed placements. Experimental results on commercial multi-core CPU designs demonstrate that our framework improves the default placement flow of Synopsys IC Compiler II (ICC2) by 3.9% in wirelength, 2.8% in power, and 85.7% in performance.
放置是现代电子设计自动化(EDA)流程中最关键的问题之一,解决方案的质量主要取决于片上互连。为了实现目标闭包,设计人员经常执行多次放置迭代来优化关键参数,如无线和定时,这非常耗时且计算效率低下。为了克服这个问题,在本文中,我们提出了一个名为PL-GNN的基于图学习的框架,该框架通过基于逻辑亲和力和设计实例的手动定义属性生成细胞簇,为商业砂矿提供放置指导。将聚类信息作为软放置约束,商业工具将努力在全局和详细放置期间将设计实例放在一起的公共组中。在商用多核CPU设计上的实验结果表明,我们的框架将Synopsys IC Compiler II (ICC2)的默认放置流提高了3.9%的带宽,2.8%的功耗和85.7%的性能。