P. Landman, A. Yee, R. Gu, B. Parthasarathy, V. Gupta, S. Ramaswamy, L. Dyson, P. Bosshart, J. Reynolds, M. Frannhagen, P. Fremrot, S. Johansson, K. Lewis, W. Lee
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引用次数: 17
Abstract
A backplane interconnect ASIC with 62 Gb/s full-duplex aggregate throughput uses 3.1 Gb/s serial link technology organized as 20 bidirectional channels to realize bandwidth. The chip operates with <5/spl times/10/sup 17/ aggregate BER and is fabricated in a 0.18 /spl mu/m CMOS technology, dissipating 9 W in a 768-pin flipchip BGA package.
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