VLSI design in heuristic environment

Abstract

Improvement in the system design process by embedding performance analysis based on heuristics is discussed. The heuristic models are used to guide the design process and help reduce the number iterations required to make a design match its specifications. Hierarchical composition is used to propagate the performance measures of any abstraction level on a bottom-up basis. An example is given for the delay performance measure of MOS VLSI systems. Experimental results for this delay prediction tool show a speedup of many orders of magnitude over simulation on large circuits.<>