TSVs-aware floorplanning for 3D integrated circuit

Abstract

3D integrated technique gives a promising method of overcoming the increasing problems of interconnect wire length and power consumption. In the design of the 3D-IC, the floorplanning algorithm decides the performance of the circuit. In this paper, we present a floorplanning algorithm considering both the critical wire length and the number of TSVs. Finally MCNC floorplan circuits are used as benchmarks. The result shows that the algorithm can reduce the critical wire length by average 40.1% and reduce the TSVs' number by 24.8% under the same critical length. The algorithm can be widely used in the design of 3D integrated circuits.