S. Barraud, V. Lapras, B. Previtali, M. Samson, J. Lacord, S. Martinie, M. Jaud, S. Athanasiou, F. Triozon, O. Rozeau, J. Hartmann, C. Vizioz, C. Comboroure, F. Andrieu, J. Barbe, M. Vinet, T. Ernst
{"title":"Performance and design considerations for gate-all-around stacked-NanoWires FETs","authors":"S. Barraud, V. Lapras, B. Previtali, M. Samson, J. Lacord, S. Martinie, M. Jaud, S. Athanasiou, F. Triozon, O. Rozeau, J. Hartmann, C. Vizioz, C. Comboroure, F. Andrieu, J. Barbe, M. Vinet, T. Ernst","doi":"10.1109/IEDM.2017.8268473","DOIUrl":null,"url":null,"abstract":"This paper presents recent progress on Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs. Key technological challenges will be discussed and recent research results presented. Width-dependent carrier mobility in Si NW/NS and FinFET will be analyzed, and intrinsic performance and design considerations of GAA structures will be discussed and compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options. The results show that more flexibility can be achieved with stacked-NS transistors in order to manage power-performance optimization.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"226 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"81","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2017.8268473","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 81
Abstract
This paper presents recent progress on Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs. Key technological challenges will be discussed and recent research results presented. Width-dependent carrier mobility in Si NW/NS and FinFET will be analyzed, and intrinsic performance and design considerations of GAA structures will be discussed and compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options. The results show that more flexibility can be achieved with stacked-NS transistors in order to manage power-performance optimization.
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