System-level test coverage prediction by structural stress test data mining

Abstract

To achieve high quality of silicon ICs, system-level test (SLT) can be performed after regular final test. This is important for chips manufactured in advanced technologies, as systematic failures are getting harder to detect by conventional structural tests. However, due to long test time and extra human efforts, the cost for SLT is high. A possible way to replace SLT without quality loss is to identify SLT failure suspects with stress tests. In this work, we apply 60,000 structural stress test patterns to the CPU blocks of a real SOC product, using 20 stressed voltage-frequency corners. We try to identify the correlation between the stress test data and SLT-pass/fail results of the CPU blocks. By the proposed differential feature-based methodology, 32 outliers are identified, which are assumed to be CPU-fail chips. Because of the lack of exact CPU-fail chip IDs for verification, the identified chip IDs are compared with the IDs identified from previous works, which use the same data but different machine-learning features and method for the same purpose. After comparison, 30 out of a total of 33 CPU-fail suspects matched. Although this does not immediately imply that the SLT can be replaced by the structural stress tests, it shows more evidence that test data mining can be further explored for test time reduction and/or quality improvement.