An order-recursive pipelined real-time VLSI HOS engine for system-on-chip implementation

Abstract

This paper presents a novel fully pipelined parallel processing VLSI architecture for the order-recursive estimation of higher order statistics(HOS) in real-time. Compared to other recent work in array computation of HOS this approach presents a fine-grained systolic VLSI architecture using simple arithmetic elements & delay elements. Also, compared to previous work which mostly dwelt on 4th & lower order statistics, this work presents an open ended upwardly compatible architectural engine which can generate HOS for any high order. The through-put of this proposed HOS engine is only limited by a multiplication interval. Hence using today's deep subquarter micron CMOS process technology, through-puts in the range of 500 MHz to 1 GHz can be achieved for this HOS engine.