{"title":"Assessing application areas for tunnel transistor technologies","authors":"M. Avedillo, J. Núñez","doi":"10.1109/DCIS.2015.7388581","DOIUrl":null,"url":null,"abstract":"Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, projected tunnel transistor technologies are evaluated and compared to LP and HP versions of both conventional and FinFET CMOS in terms of their power and energy in different application areas.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCIS.2015.7388581","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, projected tunnel transistor technologies are evaluated and compared to LP and HP versions of both conventional and FinFET CMOS in terms of their power and energy in different application areas.
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