Pub Date : 2015-11-25DOI: 10.1109/DCIS.2015.7388583
A. Darwish, L. G. Rocha, L. Fesquet, G. Sicard
Nowadays, research essentially tends to overcome the power consumption issue in the digital and analog domains. In this paper, we took a closer look on CMOS image sensors. The sensor consumption mainly depends on the image resolution. In other words, the sensor data flow is always constant regardless the activity or the scene in question. This leads to a great amount of useless data to process, store and later on display. Therefore we rethought the image sensor functioning as well as its reading method in order to reduce the sensor data flow and thus its power consumption. A novel asynchronous image sensor has been proposed using a new sampling scheme, a specific processing and an asynchronous reading technique. On one hand, the idea mainly consists of limiting the processing by only extracting the relevant data. On the other hand, the sampling method eliminates the spatial redundancies in the captured scene. Finally, by implementing the proposed reading system, we were able to drastically reduce the sensor data flow and, consequently, to design a power-efficient asynchronous image sensor.
{"title":"Design of a fully asynchronous image sensor reading system","authors":"A. Darwish, L. G. Rocha, L. Fesquet, G. Sicard","doi":"10.1109/DCIS.2015.7388583","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388583","url":null,"abstract":"Nowadays, research essentially tends to overcome the power consumption issue in the digital and analog domains. In this paper, we took a closer look on CMOS image sensors. The sensor consumption mainly depends on the image resolution. In other words, the sensor data flow is always constant regardless the activity or the scene in question. This leads to a great amount of useless data to process, store and later on display. Therefore we rethought the image sensor functioning as well as its reading method in order to reduce the sensor data flow and thus its power consumption. A novel asynchronous image sensor has been proposed using a new sampling scheme, a specific processing and an asynchronous reading technique. On one hand, the idea mainly consists of limiting the processing by only extracting the relevant data. On the other hand, the sampling method eliminates the spatial redundancies in the captured scene. Finally, by implementing the proposed reading system, we were able to drastically reduce the sensor data flow and, consequently, to design a power-efficient asynchronous image sensor.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116722525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-25DOI: 10.1109/DCIS.2015.7388588
Rabih Kazma, O. Rossetto, G. Sicard
In this paper, a novel readout method to enhance the readout dynamic range of pixel based on single photon avalanche photodiode (SPAD), is presented. This method overcomes the limitation of existing methods by using a double readout technique based on both time and amplitude measurements without decreasing the fill factor. Another advantage of the proposed method is that this improvement on the dynamic range is achieved without adding extra electronics. The proposed architecture of pixel is based on analog counter.
{"title":"High dynamic range readout architecture for SPAD array","authors":"Rabih Kazma, O. Rossetto, G. Sicard","doi":"10.1109/DCIS.2015.7388588","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388588","url":null,"abstract":"In this paper, a novel readout method to enhance the readout dynamic range of pixel based on single photon avalanche photodiode (SPAD), is presented. This method overcomes the limitation of existing methods by using a double readout technique based on both time and amplitude measurements without decreasing the fill factor. Another advantage of the proposed method is that this improvement on the dynamic range is achieved without adding extra electronics. The proposed architecture of pixel is based on analog counter.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116552110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388602
T. Domingues, Marcelino B. Santos, G. Tavares
This paper presents a technical solution for a audio player based on Click Modulation, capable of generating a PWM output out of a pre generated audio file. This modulation allows a spurious-free baseband with very low PWM switching rates. The player is based on a Texas Instrument (TI) C2000 32-bit microcontroller, that provides high resolution PWM generation with low system clock and very competitive price. Off-line Click Modulation and typical PWM modulation solutions (NPWM and USPWM) are also reported. In addition, overview of two analytical approaches for PWM spectrum determination and its results are used to help the different process used to generate the tested signals. Also a numerical approach is used for PWM spectrum determination. The experimental results of the off-line modulations used validate the theoretical and the numerical models used.
{"title":"A Click Modulation audio player","authors":"T. Domingues, Marcelino B. Santos, G. Tavares","doi":"10.1109/DCIS.2015.7388602","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388602","url":null,"abstract":"This paper presents a technical solution for a audio player based on Click Modulation, capable of generating a PWM output out of a pre generated audio file. This modulation allows a spurious-free baseband with very low PWM switching rates. The player is based on a Texas Instrument (TI) C2000 32-bit microcontroller, that provides high resolution PWM generation with low system clock and very competitive price. Off-line Click Modulation and typical PWM modulation solutions (NPWM and USPWM) are also reported. In addition, overview of two analytical approaches for PWM spectrum determination and its results are used to help the different process used to generate the tested signals. Also a numerical approach is used for PWM spectrum determination. The experimental results of the off-line modulations used validate the theoretical and the numerical models used.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130371780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388566
D. Diaz-Chinea, H. García-Vázquez, M. San Miguel Montesdeoca, S. Khemchandani, J. del Pino
In this paper, a Wide-band CMOS low-noise amplifier (LNA) based on Current Conveyors (CC) is presented, in which the thermal noise of the input MOSFET is cancelled by exploiting a noise-cancelling technique. This new LNA offers the following notable advantages over existing topologies: wideband performance, with a stable frequency response from 0 to 6.2GHz and wideband input matched impedance with a total absence of passive elements; a low Noise Figure (NF) and high linearity. Comparisons with other topologies prove the effectiveness of the new implementation.
{"title":"A Wide-band noise-cancelling CMOS LNA based on Current Conveyors","authors":"D. Diaz-Chinea, H. García-Vázquez, M. San Miguel Montesdeoca, S. Khemchandani, J. del Pino","doi":"10.1109/DCIS.2015.7388566","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388566","url":null,"abstract":"In this paper, a Wide-band CMOS low-noise amplifier (LNA) based on Current Conveyors (CC) is presented, in which the thermal noise of the input MOSFET is cancelled by exploiting a noise-cancelling technique. This new LNA offers the following notable advantages over existing topologies: wideband performance, with a stable frequency response from 0 to 6.2GHz and wideband input matched impedance with a total absence of passive elements; a low Noise Figure (NF) and high linearity. Comparisons with other topologies prove the effectiveness of the new implementation.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123855352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388586
H. Solar, Maykel Alonso, Paul Bustamante, C. Giers
This paper discusses the different steps that must be followed for the design of a Wireless Power Transfer receiver implementing an ad-hoc coil. The Wireless Power Transfer receiver follows the Qi standard but the receiver coil geometry is constrained by the application so that the coupling factor is degraded. Careful load-line simulation and validations tests show that it is possible to design a compact receiver with low coupling factor based on the Qi standard.
{"title":"Design of a Wireless Power Transfer receiver with an ad-hoc coil for the Qi Standard","authors":"H. Solar, Maykel Alonso, Paul Bustamante, C. Giers","doi":"10.1109/DCIS.2015.7388586","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388586","url":null,"abstract":"This paper discusses the different steps that must be followed for the design of a Wireless Power Transfer receiver implementing an ad-hoc coil. The Wireless Power Transfer receiver follows the Qi standard but the receiver coil geometry is constrained by the application so that the coupling factor is degraded. Careful load-line simulation and validations tests show that it is possible to design a compact receiver with low coupling factor based on the Qi standard.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130089707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388580
A. Amaricai, N. Cucu-Laurenciu, O. Boncalo, Joyan Chen, S. Nimara, V. Savin, S. Cotofana
This paper proposes a methodology for timing error analysis of RTL circuit descriptions. The evaluation has three components: (i) statistical static timing analysis (SSTA) for standard cell components (ii) estimation based on probability density function (PDF) propagation for characterization of combinational blocks, and (iii) simulated fault injection (SFI) performed at RTL. Reliability characterization of basic components is derived using SSTA; PDF propagation is used to accurately capture the probabilistic error profile of each primary output (PO) of combinational blocks; RTL saboteur based SFI is employed in order to assess the reliability of the whole circuit. The proposed methodology is applied for the fault tolerance analysis of a flooded Min-Sum (MS) LDPC decoder.
{"title":"Multi-level probabilistic timing error reliability analysis using a circuit dependent fault map generation","authors":"A. Amaricai, N. Cucu-Laurenciu, O. Boncalo, Joyan Chen, S. Nimara, V. Savin, S. Cotofana","doi":"10.1109/DCIS.2015.7388580","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388580","url":null,"abstract":"This paper proposes a methodology for timing error analysis of RTL circuit descriptions. The evaluation has three components: (i) statistical static timing analysis (SSTA) for standard cell components (ii) estimation based on probability density function (PDF) propagation for characterization of combinational blocks, and (iii) simulated fault injection (SFI) performed at RTL. Reliability characterization of basic components is derived using SSTA; PDF propagation is used to accurately capture the probabilistic error profile of each primary output (PO) of combinational blocks; RTL saboteur based SFI is employed in order to assess the reliability of the whole circuit. The proposed methodology is applied for the fault tolerance analysis of a flooded Min-Sum (MS) LDPC decoder.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134052521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388568
Hugo B. Goncalves, Jorge R. Fernandes
This paper presents a highly sensitive RF energy harvester. The developed prototype is based on an improved rectifier, that makes use of passive self compensation and biasing techniques to increase the sensitivity and efficiency of the device. These techniques include gate compensation and bulk DC biasing to lower the rectifier transistors threshold voltage. The rectifier exhibits a very high sensitivity of 84 mV at 1 V / 1 μW output voltage and power.
本文介绍了一种高灵敏度射频能量采集器。开发的原型是基于改进的整流器，它利用无源自补偿和偏置技术来提高器件的灵敏度和效率。这些技术包括栅极补偿和整体直流偏置，以降低整流晶体管的阈值电压。该整流器在1 V / 1 μW输出电压和功率下具有84 mV的高灵敏度。
{"title":"Highly sensitive RF energy harvester using gate and bulk self compensation techniques","authors":"Hugo B. Goncalves, Jorge R. Fernandes","doi":"10.1109/DCIS.2015.7388568","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388568","url":null,"abstract":"This paper presents a highly sensitive RF energy harvester. The developed prototype is based on an improved rectifier, that makes use of passive self compensation and biasing techniques to increase the sensitivity and efficiency of the device. These techniques include gate compensation and bulk DC biasing to lower the rectifier transistors threshold voltage. The rectifier exhibits a very high sensitivity of 84 mV at 1 V / 1 μW output voltage and power.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133642213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388567
Mohamed Amine Boussadi, T. Tixier, A. Landrault, J. Derutin
The gap of execution time between software and hardware computing is significant and becomes more and more important when precision is required as it is the case for the floating point calculation. This paper presents the addition of a Floating Point Unit (FPU) module to an open-source processor called SecretBlaze. Besides the description of the chosen processor enhanced by FPU thanks to user instructions, this work focuses on the hardware method to add the scalable FPU system. As a first step, design implementations enable to compare chosen FPU with other FPU available in the open-source community. It also enables to evaluate the performance of the FPU added to the processor. As a second step, we present an FPU control unit added to the architecture in order to realize several functions with few resources. All proposed architectures have been implemented and tested on FPGA target.
{"title":"A control unit module for a scalable floating-point-unit architecture","authors":"Mohamed Amine Boussadi, T. Tixier, A. Landrault, J. Derutin","doi":"10.1109/DCIS.2015.7388567","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388567","url":null,"abstract":"The gap of execution time between software and hardware computing is significant and becomes more and more important when precision is required as it is the case for the floating point calculation. This paper presents the addition of a Floating Point Unit (FPU) module to an open-source processor called SecretBlaze. Besides the description of the chosen processor enhanced by FPU thanks to user instructions, this work focuses on the hardware method to add the scalable FPU system. As a first step, design implementations enable to compare chosen FPU with other FPU available in the open-source community. It also enables to evaluate the performance of the FPU added to the processor. As a second step, we present an FPU control unit added to the architecture in order to realize several functions with few resources. All proposed architectures have been implemented and tested on FPGA target.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128838320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388591
E. Castillo, D. Morales, A. Martínez-Olmos, D. Alvarez, L. Parrilla, A. Palma, F. Navello
A FPGA dedicated processor for the digital processing of the acquired signal in electrical capacitance tomography systems is presented. The objective of this IP core is to generate an adaptable and portable prototype which is meant to work with the acquisition electronics, i.e., this whole system offers an instrument suitable to be easily transported and applied to different ECT sensors and scenarios with no need of hardware redesign. A previous developed prototype of the acquisition electronics based on a Programmable System on Chip (PSoC) has been used for the readings of the inter-electrode capacitance values. The measurements are sent through a serial communication to an FPGA, where the permittivity distribution is reconstructed using a VHDL design.
{"title":"Parametrized ECT processing over FPGA for a reconfigurable application","authors":"E. Castillo, D. Morales, A. Martínez-Olmos, D. Alvarez, L. Parrilla, A. Palma, F. Navello","doi":"10.1109/DCIS.2015.7388591","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388591","url":null,"abstract":"A FPGA dedicated processor for the digital processing of the acquired signal in electrical capacitance tomography systems is presented. The objective of this IP core is to generate an adaptable and portable prototype which is meant to work with the acquisition electronics, i.e., this whole system offers an instrument suitable to be easily transported and applied to different ECT sensors and scenarios with no need of hardware redesign. A previous developed prototype of the acquisition electronics based on a Programmable System on Chip (PSoC) has been used for the readings of the inter-electrode capacitance values. The measurements are sent through a serial communication to an FPGA, where the permittivity distribution is reconstructed using a VHDL design.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114804704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388614
J. M. Carrillo, R. Pérez-Aloe, J. L. Ausín, J. Duque, P. Carmona
Nowadays higher education degrees are repeatedly audited, internal and externally, in order to achieve continuous improvement. National and international certificates, such as EUR-ACE®, are accreditation systems used to identify high quality engineering degree programs in Europe and abroad. Currently the Master Degree in Industrial Engineering is being implanted in the University of Extremadura (UEx). A quality assurance system, as the one designed in the Industrial Engineering School of the UEx, may be used to coordinate the implantation and development of the master degree. The Process of Teaching applied to courses with contents in electronics is detailed.
{"title":"Coordination of electronics courses of the Master Degree in Industrial Engineering by means of a quality assurance system","authors":"J. M. Carrillo, R. Pérez-Aloe, J. L. Ausín, J. Duque, P. Carmona","doi":"10.1109/DCIS.2015.7388614","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388614","url":null,"abstract":"Nowadays higher education degrees are repeatedly audited, internal and externally, in order to achieve continuous improvement. National and international certificates, such as EUR-ACE®, are accreditation systems used to identify high quality engineering degree programs in Europe and abroad. Currently the Master Degree in Industrial Engineering is being implanted in the University of Extremadura (UEx). A quality assurance system, as the one designed in the Industrial Engineering School of the UEx, may be used to coordinate the implantation and development of the master degree. The Process of Teaching applied to courses with contents in electronics is detailed.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122029267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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