FPGA-Based Hardware Acceleration Using PYNQ-Z2

Vineeth C Johnson, Jyoti S. Bali, Shilpa Tanvashi, C. B. Kolanur
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Abstract

A study on the FPGA development board PYNQ-Z2 for hardware acceleration is presented in this research paper. The experiment accelerates the tasks of optical character recognition (OCR) and image recognition using the FPGA on PYNQ-Z2. The output results on hardware acceleration (Processing system (PS) and Programmable Logic (PL)) are compared with the output results obtained while executing the same tasks on the Arm processor (Processing System (PS)) alone. In this experiment, a Long short-term memory (LSTM) neural network is used to implement OCR, and a Binarized neural network (BNN) is used to implement image recognition. LSTM and BNN here are quantized to reduce memory usage while implementing them on PYNQ-Z2.
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基于fpga的PYNQ-Z2硬件加速
本文对FPGA开发板PYNQ-Z2进行了硬件加速研究。实验利用PYNQ-Z2上的FPGA加速了光学字符识别(OCR)和图像识别任务。将硬件加速(处理系统(PS)和可编程逻辑(PL))上的输出结果与单独在Arm处理器(处理系统(PS))上执行相同任务时获得的输出结果进行比较。本实验采用长短期记忆(LSTM)神经网络实现OCR,二值化神经网络(BNN)实现图像识别。在PYNQ-Z2上实现LSTM和BNN时,这里的LSTM和BNN被量化以减少内存使用。
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