Vineeth C Johnson, Jyoti S. Bali, Shilpa Tanvashi, C. B. Kolanur
{"title":"FPGA-Based Hardware Acceleration Using PYNQ-Z2","authors":"Vineeth C Johnson, Jyoti S. Bali, Shilpa Tanvashi, C. B. Kolanur","doi":"10.1109/ICEEICT56924.2023.10157764","DOIUrl":null,"url":null,"abstract":"A study on the FPGA development board PYNQ-Z2 for hardware acceleration is presented in this research paper. The experiment accelerates the tasks of optical character recognition (OCR) and image recognition using the FPGA on PYNQ-Z2. The output results on hardware acceleration (Processing system (PS) and Programmable Logic (PL)) are compared with the output results obtained while executing the same tasks on the Arm processor (Processing System (PS)) alone. In this experiment, a Long short-term memory (LSTM) neural network is used to implement OCR, and a Binarized neural network (BNN) is used to implement image recognition. LSTM and BNN here are quantized to reduce memory usage while implementing them on PYNQ-Z2.","PeriodicalId":345324,"journal":{"name":"2023 Second International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 Second International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEEICT56924.2023.10157764","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A study on the FPGA development board PYNQ-Z2 for hardware acceleration is presented in this research paper. The experiment accelerates the tasks of optical character recognition (OCR) and image recognition using the FPGA on PYNQ-Z2. The output results on hardware acceleration (Processing system (PS) and Programmable Logic (PL)) are compared with the output results obtained while executing the same tasks on the Arm processor (Processing System (PS)) alone. In this experiment, a Long short-term memory (LSTM) neural network is used to implement OCR, and a Binarized neural network (BNN) is used to implement image recognition. LSTM and BNN here are quantized to reduce memory usage while implementing them on PYNQ-Z2.