Prantik Mahajan, Vishal Ganesan, N. Subramani, Ruchil Jain, S. Mitra, R. Gauthier
{"title":"High-Voltage Electrostatic Discharge Protection Device development in 28nm BCDLite Technology","authors":"Prantik Mahajan, Vishal Ganesan, N. Subramani, Ruchil Jain, S. Mitra, R. Gauthier","doi":"10.1109/IPFA55383.2022.9915731","DOIUrl":null,"url":null,"abstract":"Best-in-class (BIC) High-Voltage (HV) Electrostatic Discharge (ESD) solutions for 8-12V power pad protection in first-of-its-kind GlobalFoundries® 28nm low-cost BCDLite process are evaluated. A comparative analysis between different types of devices, namely gate-grounded NMOS (GGNMOS), NPN, PNP and Diode, showing DC & 100ns Transmission Line Pulse (TLP) performance from Technology Computer-Aided Design (TCAD) simulations and silicon measurement results with performance metrics in terms of core device ESD protection effectiveness w.r.t Safe Operating Area (SOA) boundary and key Figures of Merit (FOMs) is elucidated.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA55383.2022.9915731","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Best-in-class (BIC) High-Voltage (HV) Electrostatic Discharge (ESD) solutions for 8-12V power pad protection in first-of-its-kind GlobalFoundries® 28nm low-cost BCDLite process are evaluated. A comparative analysis between different types of devices, namely gate-grounded NMOS (GGNMOS), NPN, PNP and Diode, showing DC & 100ns Transmission Line Pulse (TLP) performance from Technology Computer-Aided Design (TCAD) simulations and silicon measurement results with performance metrics in terms of core device ESD protection effectiveness w.r.t Safe Operating Area (SOA) boundary and key Figures of Merit (FOMs) is elucidated.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
