Characterisation of Unclamped Inductive Switching in SiC Cascode JFETs

Abstract

SiC cascode devices combine the gate input characteristics of a low voltage silicon MOSFET with the high voltage performance of a SiC JFET. Hence, SiC cascode JFETs avoid the challenges of reduced gate oxide reliability in SiC MOSFETs. SiC cascode JFETs show superior switching performance compared to SiC planar and trench MOSFETs in the same voltage rating. Avalanche ruggedness under unclamped inductive switching is an important robustness metric since it measures how well the power device can sustain power shocks from anomalous operation. In this paper, the avalanche ruggedness of SiC cascode JFETs is presented. Due to the recent commercial availability of SiC cascode JFETs, the avalanche ruggedness of these devices has not been analysed in comparison with contemporary SiC MOSFETs. Some interesting characteristics regarding the maximum energy the device can dissipate without electrothermal failure at higher temperatures are presented. In standard MOSFETs, the probability of latching the parasitic BJT during avalanche mode conduction increases with temperature, hence, avalanche ruggedness reduces at higher junction temperatures. However, in the cascode JFET, the measurements of avalanche ruggedness at high temperatures show some non-linearity due to interactions between the low voltage MOSFET and the SiC JFET. The embedded gate resistance of the SiC JFET plays a crucial role during avalanche mode conduction. Finite element simulations show that the interaction between the JFET and the low voltage MOSFET plays a critical role in UIS operation and is responsible for this observation.