Design & analysis of novel comparator without biasing for high performance application

P. V. Satya Challayya Naidu, Neeru Agarwal, Neeraj Agarwal
{"title":"Design & analysis of novel comparator without biasing for high performance application","authors":"P. V. Satya Challayya Naidu, Neeru Agarwal, Neeraj Agarwal","doi":"10.1109/ISNE.2016.7543372","DOIUrl":null,"url":null,"abstract":"Comparator have important role in ADC as which generates valid signal to the clock generator as well as compares the DAC output. Speed and the resolution is determined by the comparator, so, it is most important part in the SAR ADC. Comparator act as input signal to the clock generator as well as the compares DAC output in SAR ADC. In this paper, the analysis of the different dynamic comparator and propose a better structure, which can run faster and provide more stable output signal than the traditional structures. Comparator is designed in 180nm CMOS technology and analyzed using Node analysis.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISNE.2016.7543372","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

Comparator have important role in ADC as which generates valid signal to the clock generator as well as compares the DAC output. Speed and the resolution is determined by the comparator, so, it is most important part in the SAR ADC. Comparator act as input signal to the clock generator as well as the compares DAC output in SAR ADC. In this paper, the analysis of the different dynamic comparator and propose a better structure, which can run faster and provide more stable output signal than the traditional structures. Comparator is designed in 180nm CMOS technology and analyzed using Node analysis.
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高性能应用新型无偏置比较器的设计与分析
比较器在ADC中起着重要的作用,它为时钟发生器产生有效的信号,并对DAC的输出进行比较。速度和分辨率由比较器决定,是SAR ADC中最重要的部分。比较器作为时钟发生器的输入信号,也作为SAR ADC的比较DAC输出信号。本文对不同的动态比较器进行了分析,提出了一种更好的结构,能够比传统结构运行更快,提供更稳定的输出信号。比较器采用180nm CMOS工艺设计,采用节点分析法进行分析。
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