{"title":"A low power 60GHz OOK transceiver system in 90nm CMOS with innovative on-chip AMC antenna","authors":"F. Lin, J. Brinkhoff, K. Kang, D. Pham, X. Yuan","doi":"10.1109/ASSCC.2009.5357167","DOIUrl":null,"url":null,"abstract":"Building on an efficient active and passive device modeling strategy, a 60 GHz OOK transceiver system including on-chip antenna in 90nm CMOS is designed. The key features of the circuits are small power consumption and size. With the modulator connected to an innovative artificial magnetic conductor (AMC) on-chip antenna, free space transmission at 2Gb/s is demonstrated. Also, an on-chip psuedo-link demonstrates 1Gb/s transmission, using only 26 pJ/bit for the modulator and 6 pJ/bit for the demodulator. The receiver consists of on-chip antenna, LNA with 20dB gain & 5.7dB noise figure, detector and limiting amplifier. Recovery of a 1.5Gb/s NRZ signal is demonstrated.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"35","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2009.5357167","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 35
Abstract
Building on an efficient active and passive device modeling strategy, a 60 GHz OOK transceiver system including on-chip antenna in 90nm CMOS is designed. The key features of the circuits are small power consumption and size. With the modulator connected to an innovative artificial magnetic conductor (AMC) on-chip antenna, free space transmission at 2Gb/s is demonstrated. Also, an on-chip psuedo-link demonstrates 1Gb/s transmission, using only 26 pJ/bit for the modulator and 6 pJ/bit for the demodulator. The receiver consists of on-chip antenna, LNA with 20dB gain & 5.7dB noise figure, detector and limiting amplifier. Recovery of a 1.5Gb/s NRZ signal is demonstrated.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
