An effective distributed BIST architecture for RAMs

Abstract

The present paper proposes a solution to the problem of testing a system containing many distributed memories of different sizes. The proposed solution relies in the development of a BIST architecture characterized by a single BIST processor, implemented as a microprogrammable machine and able to execute different test algorithms, a wrapper for each SRAM including standard memory BIST modules, and an interface block to manage the communications between the SRAM and the BIST processor. Both area overhead and routing costs are minimized, and a scan-based approach allows full diagnostic capabilities of the faults possibly detected in the memories under test.