A scalable low-complexity digit-serial VLSI architecture for RSA cryptosystem

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI:10.1109/SIPS.1999.822365

Jye-Jong Leu, A. Wu

引用次数: 10

Abstract

The Booth-encoded Montgomery modular multiplication algorithm is proposed to reduce the iteration number to about n/2 in each Montgomery operation. In addition, we apply the folding and unfolding technique to shorten the critical path. Finally, we propose the 2 bit-digit-serial pipelined architecture to process RSA en/decryption in a more efficient way. By applying the proposed algorithm in RSA design, the hardware complexity can be reduced by 15% compared with most RSA VLSI designs using the Montgomery modular multiplication algorithm.

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RSA密码系统的可扩展低复杂度数字串行VLSI架构

提出了booth编码Montgomery模乘法算法，将每次Montgomery运算的迭代次数减少到n/2左右。此外，我们还应用了折叠和展开技术来缩短关键路径。最后，我们提出了2位数字串行流水线架构，以更有效的方式处理RSA加密/解密。通过将该算法应用于RSA设计，与使用Montgomery模乘法算法的大多数RSA VLSI设计相比，硬件复杂度可降低15%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)

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