{"title":"Millimeter-wave VNA Calibration using a CMOS Transmission Line with Distributed Switches","authors":"Jun-Chau Chien","doi":"10.1109/RFIC54546.2022.9863095","DOIUrl":null,"url":null,"abstract":"This paper presents a single-element VNA electronic calibration (E-Cal) technique implemented in CMOS technology. The structure employs a transmission line (t-line) loaded with twenty distributed switches whose impedance states can be independently modulated during S-parameter measurements. An algorithm that leverages the implementation concepts from the one-port offset-shorts and the two-port Line-Reflect-Reflect-Match $(LRRM)$ calibrations and takes advantage of the loading periodicity and the structure layout symmetry is developed. The calibration method is justified using a 65-nm CMOS test chip and the measurement results are compared with on-chip one-tier TRL calibration using both passive and active devices up to 67 GHz.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC54546.2022.9863095","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents a single-element VNA electronic calibration (E-Cal) technique implemented in CMOS technology. The structure employs a transmission line (t-line) loaded with twenty distributed switches whose impedance states can be independently modulated during S-parameter measurements. An algorithm that leverages the implementation concepts from the one-port offset-shorts and the two-port Line-Reflect-Reflect-Match $(LRRM)$ calibrations and takes advantage of the loading periodicity and the structure layout symmetry is developed. The calibration method is justified using a 65-nm CMOS test chip and the measurement results are compared with on-chip one-tier TRL calibration using both passive and active devices up to 67 GHz.