S. Sacarisen, M. Stambaugh, P. Lou, A. Khosrovi, Ki Chang
{"title":"A VLSI communication processor designed for testability","authors":"S. Sacarisen, M. Stambaugh, P. Lou, A. Khosrovi, Ki Chang","doi":"10.1109/ISSCC.1984.1156646","DOIUrl":null,"url":null,"abstract":"A 16b processor for control of digital communication networks, with 2186 bytes of RAM will be discussed. The chip features include instruction fault detection, I/O parity check/ generation and special test modes.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1984.1156646","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A 16b processor for control of digital communication networks, with 2186 bytes of RAM will be discussed. The chip features include instruction fault detection, I/O parity check/ generation and special test modes.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
