A 105 dB SNR multibit /spl Sigma//spl Delta/ ADC for digital audio applications

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-09 DOI:10.1109/CICC.2001.929717

K. Nguyen, B. Adams, K. Sweetland

引用次数: 4

Abstract

A four-channel multibit /spl Sigma//spl Delta/ analog-to-digital converter (ADC) for consumer audio applications is described. The converter uses a second order switched-capacitor modulator with a 4-bit quantizer and a noise-shaped scrambler for dynamic element matching. To achieve the target settling time with reduced power consumption, the opamps are dynamically compensated. A multi-stage decimation filter with adjustable front-end sine filter is used to produce the PCM output at a selectable sample rate of 48/96 kHz. The converter achieves an SNR and D-range of 105 dB (A-weighted), THD+N of -98 dB at 48 kHz sample rate. The circuit is implemented in 0.5 /spl mu/m DPTM CMOS, dissipating 90 mW per channels. The core die size is 1.6 mm/sup 2/ per channel.

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用于数字音频应用的105 dB信噪比多位/spl Sigma//spl Delta/ ADC

描述了一种用于消费音频应用的四通道多位/spl Sigma//spl Delta/模数转换器(ADC)。该变换器采用带4位量化器的二阶开关电容调制器和用于动态元件匹配的噪声型扰频器。为了在降低功耗的情况下达到目标稳定时间，对运放大器进行了动态补偿。具有可调前端正弦滤波器的多级抽取滤波器用于产生48/96 kHz可选采样率的PCM输出。在48 kHz采样率下，该转换器的信噪比和d范围为105 dB (a加权)，THD+N为-98 dB。该电路采用0.5 /spl mu/m DPTM CMOS实现，每个通道耗散90 mW。芯模尺寸为1.6 mm/sup 2/每通道。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

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