A Systemc Test Environment For Spin Network

Abstract

Evaluate system on-chip architectures necessitates test boards and applications. For the comparison between the packet-switched micro-network SPIN and the traditional Pi-Bus we have elaborated SystemC components and multi-threads programs. Instead of using a traffic generator analyzer, component flooding the network with packets, we use a true application running on processor MIPS R3000. By that way we have a various traffic much more realistic. This article describes the way to manage the SystemC simulation and gives details about the structure of an application saturating the Pi-Bus. The results show the importance of an increasing bandwith when we use a parallel application, and also reveal the difficulty we can have to saturate the SPIN network with processors