Dynamic Simulation of Write ‘1’ Operation in the Bi-stable 1-Transistor SRAM Cell

Abstract

For the first time, physical insights into the writing process in the bi-stable 1-transistor SRAM cells are provided using dynamic (time dependent) TCAD simulations. The simulations are based on 28 nm planar CMOS technology, and the setup is carefully calibrated against available experimental data. Based on the simulations, we were able to identify clearly the mechanisms involved in the write ‘1’ operation. The dependence of the writing process on drain and gate bias conditions was also investigated.