Performance Enhancement of Non-uniformly Doped Junctionless Transistors by Gate and Dielectric engineering

Muktasha Maji, Gaurav Saini
{"title":"Performance Enhancement of Non-uniformly Doped Junctionless Transistors by Gate and Dielectric engineering","authors":"Muktasha Maji, Gaurav Saini","doi":"10.1109/DEVIC.2019.8783415","DOIUrl":null,"url":null,"abstract":"In this paper, the use of laterally graded doping and hetero gate high dielectric with high-k spacers which were positioned on both sides of the gate have been proposed to improve the performance of Junctionless Transistors (JLT). Further recessed gate structure is also used to compare its performance with conventional JLTs. 2-D TCAD simulations have been used to observe that the Drain-Induced Barrier Lowering (DIBL) and Sub Threshold Swing (SS) were reduced by 26% and 61% respectively. Further the current ratio improved by 108 times in the final structure. Our analysis focuses on the ability of the proposed design for a reduced leakage current leading to higher current ratio and also lower short channel effects (SCEs) like SS and DIBL.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Devices for Integrated Circuit (DevIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DEVIC.2019.8783415","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

In this paper, the use of laterally graded doping and hetero gate high dielectric with high-k spacers which were positioned on both sides of the gate have been proposed to improve the performance of Junctionless Transistors (JLT). Further recessed gate structure is also used to compare its performance with conventional JLTs. 2-D TCAD simulations have been used to observe that the Drain-Induced Barrier Lowering (DIBL) and Sub Threshold Swing (SS) were reduced by 26% and 61% respectively. Further the current ratio improved by 108 times in the final structure. Our analysis focuses on the ability of the proposed design for a reduced leakage current leading to higher current ratio and also lower short channel effects (SCEs) like SS and DIBL.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
栅极和介电工程增强非均匀掺杂无结晶体管的性能
为了提高无结晶体管的性能,本文提出了采用横向梯度掺杂和异质栅极高介电介质以及在栅极两侧设置高k间隔片的方法。进一步采用凹栅结构与传统jlt进行性能比较。通过二维TCAD模拟发现,排水诱导的屏障降低(DIBL)和亚阈值摆动(SS)分别降低了26%和61%。最终结构的电流比提高了108倍。我们的分析重点是提出的设计的能力,以减少泄漏电流,从而提高电流比,并降低短通道效应(SCEs),如SS和DIBL。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Analytical Drain Current Model of UTBB SOI MOSFET with lateral dual gates to Suppress Short Channel Effect Effect of AlGaN Back Barrier on InAlN/AlN/GaN E-Mode HEMTs Work-function modulated hetero gate charge plasma TFET to enhance the device performance All-optical Walsh-Hadamard code Generation using MZI Performance Analysis of Staggered Heterojunction based SRG TFET biosensor for health IoT application
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1