Scaling Dual-Gate Ultra-thin a-IGZO FET to 30 nm Channel Length with Record-high Gm,max of 559 µS/µm at VDS=1 V, Record-low DIBL of 10 mV/V and Nearly Ideal SS of 63 mV/dec
Kaifei Chen, J. Niu, Guanhua Yang, Meng-xin Liu, Wendong Lu, Fuxi Liao, Kailiang Huang, Xinlv Duan, Congyan Lu, Jiawei Wang, Lingfei Wang, Mengmeng Li, Di Geng, Chao Zhao, Guilei Wang, Nianduan Lu, Ling Li, Ming Liu
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引用次数: 5
Abstract
We experimentally prove that amorphous IGZO FET can be scaled down by connected dual-gate design with enhanced electrostatic control. By connected dual-gate operation and scaled dual stacks, the short channel device (LCH=30 nm) achieves near ideal SS of 63 mV/dec and ultra-high on-state current (ION) of 615 µA/µm at VGS-VTH=2 V&VDS=1 V. By this design, record-high transconductance (Gm) of 559 µS/µm at VDS=1 V and record-low drain-induced-barrier-lowering (DIBL) of 10 mV/V are achieved, to our best knowledge, among all the a-IGZO transistors with sub-100 nm channel length reported so far.