Memory access micro-profiling for ASIP design

Abstract

The memory subsystem is the major performance bottleneck in terms of speed and power consumption in today's digital systems. This is especially true for application specific embedded systems where power consumption due to memory traffic, memory latency and size of the on-chip caches have a significant role in overall system performance, energy efficiency and cost. There is an urgent need of tools that help designers take informed decisions about memory subsystems for embedded applications. This paper presents a novel, fine-grained memory profiling technique that provides the designer with valuable information such as the total amount of dynamic memory requirement of an application, the most heavily accessed source level data objects, the most memory intensive portions of an application etc. Such information can aid designers to take decisions about the overall memory subsystem comprising of a number of different cache levels, scratch-pad memories and main memory. It can also be used by a compiler to perform advanced compiler controlled memory assignment techniques, and by the application programmer to optimize an application. Case studies at the end of this paper demonstrate the accuracy of our profiling technique and provide some example usage scenarios of it.