Verticalization Of Direct Structural Table In Synthesis Of Mealy FSMS For FPGAs

Abstract

The method of decreasing of amount of logic in FPGA device that implements the logic circuit of finite state machine (FSM) with Mealy outputs is proposed. Method is based on verticalization of microinstructions in direct structural table (DST). As a result of verticalization all microoperations of direct structural table are compatible ones. It permits to encode each microoperation by code with minimal possible number of bits. In this case only one decoder is used for implementation of the microoperations system. This method permits to minimize a number of outputs of the combinational part of Mealy FSM in comparison with the same characteristic of Mealy FSM with encoding of fields of compatible microoperations