Comparison of TSV-based PDN-design effects using various stacking topology methods

Abstract

In this study, we estimate, compare and analyze the PDN effects of four chip-stacking topologies. The chip-stacking topologies are: (1) F2B; (2) F2F; (3) B2F; and (4) B2B. The arrangement of various on-chip interconnect elements based on the chip-stacking topologies specific to the design of 3D IC-PDN, varies in impedance properties. To reduce the impedance effects NMOS decap unit cells are integrated into PDN system to suppress 3D-SSN. Conclusively, the results of the case study indicate B2F and F2B die stacking topologies results in lower impedance effects relative to F2F topology.