Predicting circuit performance using circuit-level statistical timing analysis

Abstract

Recognizing that the delay of a circuit is extremely sensitive to manufacturing process variations, this paper proposes a methodology for statistical timing analysis. The authors present a triple-node delay model which inherently captures the effect of input transition time on the gate delays. Response surface methods are used so that the statistical gate delays are generated efficiently. A new path sensitization criterion based on the minimum propagatable pulse width (MPPW) of the gates along a path is used to check for false paths. The overlap of a path with longer paths determines its "statistical significance" to the overall circuit delay. Finally, the circuit delay probability density function is computed by performing a Monte Carlo simulation on the statistically significant path set.<>