Efficient FPGA implementation of H.264 CAVLC entropy decoder

Abstract

Multiprocessor-system-on-a-chip (MPSoC) is the dominating architecture in embedded systems. Applications need to be multi-threaded to benefit from the concurrency provided by the MPSoC. Many parallel versions of the new emerging H.264/AVC [1] already exist. However, providing a full parallel H.264 version is blocked by the fact that all parts of the decoder depend on the first sequential stage of the decoding process which is the entropy decoder (mainly CAVLC). The entropy decoder consumes about 30% [8] of the total time of the decoder. In this work, we propose an optimized FPGA design achieving the demands of multi-threaded H.264 decoder versions which can be integrated in an MPSoC. We focus in our work on time optimization and on cycle number decrease when decoding an encoded 4×4 block of pixels. We also aim to achieve a design that operates at high frequencies. The work leads to the ability to decode at least 62 frames per second for HD resolution 1280×720. Decoding takes 22 clock cycles for one block of 4×4 pixels at most. The design has an upper frequency limit of 247MHz. High resolutions frames such as 1920×1088 FHD (full high definition) video maintain a minimum frequency of 30 fps.