MILEF: an efficient approach to mixed level automatic test pattern generation

Abstract

Automatic test pattern generation in CMOS circuits from gate-level net lists is efficient, but has shortcomings with respect to fault coverage in complex and irregular CMOS gates and networks. An approach relying on the transistor structure only is inefficient and virtually impossible for larger circuits. The authors describe the gate level part of a tool for dynamically coupled gate-level and switch-level test generation. Acceptable performance and high fault coverage for non-trivial transistor networks are combined. Patterns generated in this way are inherently capable of detecting interrupt types of faults and transition faults. In combination with local overcurrent detectors, stuck-on and bridging faults can be identified.<>