Kyoungrok Cho, Sang-Jin Lee, Kwang-Seok Oh, Ca-Ram Han, O. Kavehei, K. Eshraghian
{"title":"Pattern matching and classification based on an associative memory architecture using CRS","authors":"Kyoungrok Cho, Sang-Jin Lee, Kwang-Seok Oh, Ca-Ram Han, O. Kavehei, K. Eshraghian","doi":"10.1109/CNNA.2012.6331433","DOIUrl":null,"url":null,"abstract":"Emergence of new materials and in particular the recent progress in Memristor and related memory technologies encouraged the research community for a renewed approach towards formulation of architectures such as those that depend upon associate memory constructs to take the advantages being offered within this new design domain. In this paper we address a key issue in pattern matching and classification process and hence suggest an alternative approach for image vector matching combining Complementary Resistive Switch (CRS) array and bump circuits. We emulated an experimental pattern matching with two approaches which are based on Hamming distance and threshold level of the image: the former finds an exact image with a bump circuit and the later finds similar patterns from the stored images combining comparators. The proposed hardware oriented architecture is high speed and smaller size that is easier to implement on conventional CMOS technology.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CNNA.2012.6331433","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
Emergence of new materials and in particular the recent progress in Memristor and related memory technologies encouraged the research community for a renewed approach towards formulation of architectures such as those that depend upon associate memory constructs to take the advantages being offered within this new design domain. In this paper we address a key issue in pattern matching and classification process and hence suggest an alternative approach for image vector matching combining Complementary Resistive Switch (CRS) array and bump circuits. We emulated an experimental pattern matching with two approaches which are based on Hamming distance and threshold level of the image: the former finds an exact image with a bump circuit and the later finds similar patterns from the stored images combining comparators. The proposed hardware oriented architecture is high speed and smaller size that is easier to implement on conventional CMOS technology.