Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331442
C. Nemes, Z. Nagy, P. Szolgay
In the paper a framework for generating a locally controlled arithmetic unit is presented including graph generation from a mathematical expression, graph partitioning to determine locally controlled parts of the design and VHDL generation. The output of the framework is a pipelined architecture containing locally controlled groups of floating point units. It is demonstrated that both partitioning and placement aspects of the design have to be considered to obtain a highspeed circuit. In a well-placeable design locally controlled groups can be mapped to FPGA in such a way that only neighboring groups communicate with each other. In the presented algorithm an initial floorplan of the floating point units is produced and a novel graph partitioning representation is used for partitioning the floating point units to obtain a well-placeable design. The framework is demonstrated during the automatic circuit generation of a complex mathematical expression related to Computation Fluid Dynamics (CFD). The framework produces 15-27% faster design than the unpartitioned, globally controlled one in the price of a modest area increase. The framework automatically produces well-placeable deadlock-free partitions for complex expressions as well, while in case of traditional partitioners these objectives cannot be targeted.
{"title":"Automatic generation of locally controlled arithmetic unit via floorplan based partitioning","authors":"C. Nemes, Z. Nagy, P. Szolgay","doi":"10.1109/CNNA.2012.6331442","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331442","url":null,"abstract":"In the paper a framework for generating a locally controlled arithmetic unit is presented including graph generation from a mathematical expression, graph partitioning to determine locally controlled parts of the design and VHDL generation. The output of the framework is a pipelined architecture containing locally controlled groups of floating point units. It is demonstrated that both partitioning and placement aspects of the design have to be considered to obtain a highspeed circuit. In a well-placeable design locally controlled groups can be mapped to FPGA in such a way that only neighboring groups communicate with each other. In the presented algorithm an initial floorplan of the floating point units is produced and a novel graph partitioning representation is used for partitioning the floating point units to obtain a well-placeable design. The framework is demonstrated during the automatic circuit generation of a complex mathematical expression related to Computation Fluid Dynamics (CFD). The framework produces 15-27% faster design than the unpartitioned, globally controlled one in the price of a modest area increase. The framework automatically produces well-placeable deadlock-free partitions for complex expressions as well, while in case of traditional partitioners these objectives cannot be targeted.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123712528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331415
M. Janczyk, K. Slot
A concept of Cellular Neural Networks with dynamic cell activity control is proposed in the paper. The concept is an extension to the Fixed State Map mechanism and it assumes that cells can be disabled or enabled for processing based on assessment of current distributions of their neighboring signals. A particular case, where this assessment is made by thresholding a result of cross-correlation between feedback template and neighborhood outputs is shown to provide a simple means for efficient min/max problem handling. This idea requires introducing only minor modifications to a cell structure. As an example, application of the proposed network for fast estimation of Hausdorff distance between two sets has been considered.
{"title":"Cellular Neural Networks with dynamic cell activity control for Hausdorff distance estimation","authors":"M. Janczyk, K. Slot","doi":"10.1109/CNNA.2012.6331415","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331415","url":null,"abstract":"A concept of Cellular Neural Networks with dynamic cell activity control is proposed in the paper. The concept is an extension to the Fixed State Map mechanism and it assumes that cells can be disabled or enabled for processing based on assessment of current distributions of their neighboring signals. A particular case, where this assessment is made by thresholding a result of cross-correlation between feedback template and neighborhood outputs is shown to provide a simple means for efficient min/max problem handling. This idea requires introducing only minor modifications to a cell structure. As an example, application of the proposed network for fast estimation of Hausdorff distance between two sets has been considered.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122292024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331439
A. Kiss, Z. Nagy, Á. Csík, P. Szolgay
There are a large number of problems which can be accelerated by using architectures on Field Programmable Gate Arrays (FPGA). However sometimes the complexity of a problem does not allow to map it onto a specific FPGA. In that case analysis of precision of the arithmetic unit which may solve the computational problem can be a good attempt to fit the architecture and to accelerate its computation. Numerical algorithm can be implemented using fixed-point or floating point arithmetic (or mixed (both)) with different precision. The aim of the article is not to optimize the numerical algorithm but to find a smaller arithmetic unit precision, which results enough accuracy and fits to smaller FPGA-s. In the paper, one particular problem type is investigated, namely the accuracy of the solution of a simple Partial Differential Equation (PDE). The accuracy measurement is done on an FPGA with different bit width. The solution of the advection equation is analyzed using first and second order discretization methods. As a result we managed to find an optimal bit width for the solution on a specific FPGA.
{"title":"Examining the accuracy and the precision of PDEs for FPGA computations","authors":"A. Kiss, Z. Nagy, Á. Csík, P. Szolgay","doi":"10.1109/CNNA.2012.6331439","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331439","url":null,"abstract":"There are a large number of problems which can be accelerated by using architectures on Field Programmable Gate Arrays (FPGA). However sometimes the complexity of a problem does not allow to map it onto a specific FPGA. In that case analysis of precision of the arithmetic unit which may solve the computational problem can be a good attempt to fit the architecture and to accelerate its computation. Numerical algorithm can be implemented using fixed-point or floating point arithmetic (or mixed (both)) with different precision. The aim of the article is not to optimize the numerical algorithm but to find a smaller arithmetic unit precision, which results enough accuracy and fits to smaller FPGA-s. In the paper, one particular problem type is investigated, namely the accuracy of the solution of a simple Partial Differential Equation (PDE). The accuracy measurement is done on an FPGA with different bit width. The solution of the advection equation is analyzed using first and second order discretization methods. As a result we managed to find an optimal bit width for the solution on a specific FPGA.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121902958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331459
Weiran Cai, Ronald Tetzlaff
In this paper, we propose a memristive STDP model realizing the principle of suppression of Froemke and Dan for triplet spikes. The proposed model claims compatibility with both the pair and triplet STDP rules, going beyond the limit of the basic memristive STDP model. The compatibility is realized by assuming a mechanism of variable thresholds adapting to synaptic potentiation (LTP) and depression (LTD): the preceding LTP has a negative influence on the following LTD. The corresponding dynamical process is governed by a set of ordinary differential equations. It is an equivalent model of the original suppression STDP model. A relation of the adaptive thresholds to short-term plasticity is addressed.
{"title":"Advanced memristive model of synapses with adaptive thresholds","authors":"Weiran Cai, Ronald Tetzlaff","doi":"10.1109/CNNA.2012.6331459","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331459","url":null,"abstract":"In this paper, we propose a memristive STDP model realizing the principle of suppression of Froemke and Dan for triplet spikes. The proposed model claims compatibility with both the pair and triplet STDP rules, going beyond the limit of the basic memristive STDP model. The compatibility is realized by assuming a mechanism of variable thresholds adapting to synaptic potentiation (LTP) and depression (LTD): the preceding LTP has a negative influence on the following LTD. The corresponding dynamical process is governed by a set of ordinary differential equations. It is an equivalent model of the original suppression STDP model. A relation of the adaptive thresholds to short-term plasticity is addressed.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130569934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331435
V. Pham, A. Buscarino, M. Frasca, L. Fortuna, T. Hoang
Cellular Neural/Nonlinear Networks (CNNs) constitute an effective approach for studying complex phenomena like autowaves, spiral waves or pattern formation either by providing a computationally efficient environment for numerical simulations or by allowing the possibility of hardware emulators of the system under study. In this work, we focus on a CNN made of memristor-based cells, namely a Memristive Cellular Neural/Nonlinear Network (MCNN). This has been recently shown to be capable of generating complex phenomena such as autowave propagation. In this work, we implement such a MCNN by using Field Programmable Gate Array (FPGA). Our system consisting of a FPGA development board connected to a monitor allows us to emulate autowave propagation in an efficient way. Experimental results show the feasibility of FPGA-based approach to implement MCNN.
{"title":"FPGA-based generation of autowaves in Memristive Cellular Neural Networks","authors":"V. Pham, A. Buscarino, M. Frasca, L. Fortuna, T. Hoang","doi":"10.1109/CNNA.2012.6331435","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331435","url":null,"abstract":"Cellular Neural/Nonlinear Networks (CNNs) constitute an effective approach for studying complex phenomena like autowaves, spiral waves or pattern formation either by providing a computationally efficient environment for numerical simulations or by allowing the possibility of hardware emulators of the system under study. In this work, we focus on a CNN made of memristor-based cells, namely a Memristive Cellular Neural/Nonlinear Network (MCNN). This has been recently shown to be capable of generating complex phenomena such as autowave propagation. In this work, we implement such a MCNN by using Field Programmable Gate Array (FPGA). Our system consisting of a FPGA development board connected to a monitor allows us to emulate autowave propagation in an efficient way. Experimental results show the feasibility of FPGA-based approach to implement MCNN.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131071084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331426
Shahar Kvatinsky, Nimrod Wald, Guy Satat, A. Kolodny, U. Weiser, E. Friedman
Memristive devices are novel structures, developed primarily as memory. Another interesting application for memristive devices is logic circuits. In this paper, MRL (Memristor Ratioed Logic) - a hybrid CMOS-memristive logic family - is described. In this logic family, OR and AND logic gates are based on memristive devices, and CMOS inverters are added to provide a complete logic structure and signal restoration. Unlike previously published memristive-based logic families, the MRL family is compatible with standard CMOS logic. A case study of an eight-bit full adder is presented and related design considerations are discussed.
{"title":"MRL — Memristor Ratioed Logic","authors":"Shahar Kvatinsky, Nimrod Wald, Guy Satat, A. Kolodny, U. Weiser, E. Friedman","doi":"10.1109/CNNA.2012.6331426","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331426","url":null,"abstract":"Memristive devices are novel structures, developed primarily as memory. Another interesting application for memristive devices is logic circuits. In this paper, MRL (Memristor Ratioed Logic) - a hybrid CMOS-memristive logic family - is described. In this logic family, OR and AND logic gates are based on memristive devices, and CMOS inverters are added to provide a complete logic structure and signal restoration. Unlike previously published memristive-based logic families, the MRL family is compatible with standard CMOS logic. A case study of an eight-bit full adder is presented and related design considerations are discussed.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133333867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331473
S. Levitan, Yan Fang, D. Dash, T. Shibata, D. Nikonov, G. Bourianoff
Many of the proposed and emerging nano-scale technologies simply cannot compete with CMOS in terms of energy efficiency for performing Boolean operations. However, the potential for these technologies to perform useful non-Boolean computations remains an opportunity to be explored. In this talk we examine the use of the resonance of coupled nano-scale oscillators as a primitive computational operator for associative processing and develop the architectural structures that could enable such devices to be integrated into mainstream applications.
{"title":"Non-Boolean associative architectures based on nano-oscillators","authors":"S. Levitan, Yan Fang, D. Dash, T. Shibata, D. Nikonov, G. Bourianoff","doi":"10.1109/CNNA.2012.6331473","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331473","url":null,"abstract":"Many of the proposed and emerging nano-scale technologies simply cannot compete with CMOS in terms of energy efficiency for performing Boolean operations. However, the potential for these technologies to perform useful non-Boolean computations remains an opportunity to be explored. In this talk we examine the use of the resonance of coupled nano-scale oscillators as a primitive computational operator for associative processing and develop the architectural structures that could enable such devices to be integrated into mainstream applications.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124486780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331445
B. Nagy, S. Tõkés
Aberration correction using Reference Conjugated Hologram (RCH) method is investigated. However we use it not for a single but for a number of reconstructed object planes in Digital Holographic Microscopy (DHM). We build an off-axis DHM for testing the performance of the method. The limits of this method have been studied. We compare in-line with aberration compensated off-axis DHM. The in-line DHM compensates quite the same aberrations physically as the RCH method numerically.
{"title":"Study on application of Reference Conjugated Hologram for aberration correction of multiple object planes","authors":"B. Nagy, S. Tõkés","doi":"10.1109/CNNA.2012.6331445","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331445","url":null,"abstract":"Aberration correction using Reference Conjugated Hologram (RCH) method is investigated. However we use it not for a single but for a number of reconstructed object planes in Digital Holographic Microscopy (DHM). We build an off-axis DHM for testing the performance of the method. The limits of this method have been studied. We compare in-line with aberration compensated off-axis DHM. The in-line DHM compensates quite the same aberrations physically as the RCH method numerically.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125797613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331463
T. Roska, A. Horváth, A. Stubendek, F. Corinto, G. Csaba, W. Porod, T. Shibata, G. Bourianoff
An Associative Memory is built by three consecutive components: (1) a CMOS preprocessing unit generating input feature vectors from picture inputs, (2) an AM cluster generating signature outputs composed of spintronic oscillator (STO) cells and local spin-wave interactions, as an oscillatory CNN (O-CNN) array unit, applied several times arranged in space, and (3) a classification unit (CMOS). The end to end design of the preprocessing unit, the interacting O-CNN arrays, and the classification unit is embedded in a learning and optimization procedure where the geometric distances between the STOs in the O-CNN arrays play a crucial role. The O-CNN array has an input vector as a 1D array of oscillator frequencies, and the synchronized O-CNN array codes the output as the phases of the output 1D array. The typical O-CNN array has 1-3 rows of STOs. Simplified STO and interaction macro models are used. A typical example is shown using an End-to-end Simulator.
{"title":"An Associative Memory with oscillatory CNN arrays using spin torque oscillator cells and spin-wave interactions architecture and End-to-end Simulator","authors":"T. Roska, A. Horváth, A. Stubendek, F. Corinto, G. Csaba, W. Porod, T. Shibata, G. Bourianoff","doi":"10.1109/CNNA.2012.6331463","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331463","url":null,"abstract":"An Associative Memory is built by three consecutive components: (1) a CMOS preprocessing unit generating input feature vectors from picture inputs, (2) an AM cluster generating signature outputs composed of spintronic oscillator (STO) cells and local spin-wave interactions, as an oscillatory CNN (O-CNN) array unit, applied several times arranged in space, and (3) a classification unit (CMOS). The end to end design of the preprocessing unit, the interacting O-CNN arrays, and the classification unit is embedded in a learning and optimization procedure where the geometric distances between the STOs in the O-CNN arrays play a crucial role. The O-CNN array has an input vector as a 1D array of oscillator frequencies, and the synchronized O-CNN array codes the output as the phases of the output 1D array. The typical O-CNN array has 1-3 rows of STOs. Simplified STO and interaction macro models are used. A typical example is shown using an End-to-end Simulator.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130983012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331454
G. Collazuol, V. Innocente, G. Lamanna, F. Pantaleo, M. Sozzi
We describe a pilot project for the use of GPUs in a real-time triggering application in the early trigger stages at the CERN NA62 experiment, and the results of the first field tests together with a prototype data acquisition (DAQ) system. This pilot project within NA62 aims at integrating GPUs into the central L0 trigger processor, and also to use them as fast online processors for computing trigger primitives. Several TDC-equipped sub-detectors with sub-nanosecond time resolution will participate in the first-level NA62 trigger (L0), fully integrated with the data-acquisition system, to reduce the readout rate of all sub-detectors to 1 MHz, using multiplicity information asynchronously computed over time frames of a few ns, both for positive sub-detectors and for vetos. The online use of GPUs would allow the computation of more complex trigger primitives already at this first trigger level. We describe the architectures of the proposed systems, focusing on measuring the performance (both throughput and latency) of various approaches meant to solve these high energy physics problems. The challenges and the prospects of this promising idea are discussed.
{"title":"Real-time use of GPUs in NA62 experiment","authors":"G. Collazuol, V. Innocente, G. Lamanna, F. Pantaleo, M. Sozzi","doi":"10.1109/CNNA.2012.6331454","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331454","url":null,"abstract":"We describe a pilot project for the use of GPUs in a real-time triggering application in the early trigger stages at the CERN NA62 experiment, and the results of the first field tests together with a prototype data acquisition (DAQ) system. This pilot project within NA62 aims at integrating GPUs into the central L0 trigger processor, and also to use them as fast online processors for computing trigger primitives. Several TDC-equipped sub-detectors with sub-nanosecond time resolution will participate in the first-level NA62 trigger (L0), fully integrated with the data-acquisition system, to reduce the readout rate of all sub-detectors to 1 MHz, using multiplicity information asynchronously computed over time frames of a few ns, both for positive sub-detectors and for vetos. The online use of GPUs would allow the computation of more complex trigger primitives already at this first trigger level. We describe the architectures of the proposed systems, focusing on measuring the performance (both throughput and latency) of various approaches meant to solve these high energy physics problems. The challenges and the prospects of this promising idea are discussed.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125555697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：